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US 6,147,513 AGranted
Method and circuit for logic input buffer
AssigneeWinbond Electronics Corp.
InventorJohn Henry Bui
Life of this patent
Estimating the term…
Abstract
A novel logic input buffer having independent DC input trip points (e.g., V.sub.IL and V.sub.IH), reduced cross current during signal transitions, shorter propagation delay, and improved noise performance. The input buffer includes a set of input transistors having dynamically adjustable beta(s) that allows for robust control of the transistor(s) operating characteristics. The beta(s) can be adjusted by changing the size(s) of the input transistors through enabling and disabling selected one(s) of additional input transistor(s).
Claims32
A logic input buffer for receiving an input signal, comprising:
- a P-channel input transistor;
- an N-channel input transistor coupled in series with the P-channel input transistor;
- an additional input transistor coupled in parallel with one of the input transistors;
- a control transistor coupled in series with the additional input transistor, and
- wherein the additional input transistor is dynamically enabled before selective ones of rising and falling transitions of the input signal and dynamically disabled before selective other ones of transitions of the input signal, and wherein the additional input transistor is enabled or disabled for the duration of the rising and falling transitions.
2 more elements
A logic input buffer comprising:
- a P-channel input transistor;
- an N-channel input transistor coupled in series with the P-channel input transistor;
- an additional input transistor coupled in parallel with one of the input transistors and enabled before, and for the duration of, selective ones of rising and falling transitions of an input signal;
- a control transistor coupled in series with the additional input transistor;
- and
- a control circuit coupled to the control transistor and to the input signal.
3 more elements
A logic input buffer comprising:
- a P-channel input transistor;
- an N-channel input transistor coupled in series with the P-channel input transistor;
- an additional input transistor coupled in parallel with one of the input transistors and enabled before selective ones of rising and falling transitions of an input signal;
- a control transistor coupled in series with the additional input transistor;
- and
- a control circuit coupled to the control transistor and to the input signal, wherein the control circuit comprises
- a first inverter coupled to the input signal,
- a second inverter coupled to the input signal,
- a latch coupled to the first and second inverters, and
- wherein the latch couples to the control transistor.
7 more elements
A logic input buffer comprising:
- a P-channel input transistor;
- an N-channel input transistor coupled in series with the P-channel input transistor;
- an additional input transistor coupled in parallel with one of the input transistors and enabled before, and for the duration of, selective ones of rising and falling transitions of an input signal;
- a control transistor coupled in series with the additional input transistor;
- and
- a control circuit coupled to the control transistor and comprising a delay element.
3 more elements
A logic input buffer comprising:
- a P-channel input transistor;
- an N-channel input transistor coupled in series with the P-channel input transistor;
- an additional P-channel input transistor coupled in parallel with the P-channel input transistor;
- an additional N-channel input transistor coupled in parallel with the N-channel input transistor;
- a first control transistor coupled in series with the additional P-channel input transistor;
- a second control transistor coupled in series with the additional N-channel input transistor, and
- wherein the additional input transistors are each dynamically enabled before, and for the duration of, selective ones of rising and falling transitions of an input signal.
4 more elements
A logic input buffer comprising:
- a first input transistor;
- a second input transistor coupled in series with the first input transistor;
- a third input transistor coupled in parallel with one of the first and second input transistors;
- and
- a control circuit operatively coupled to the third transistor and the input signal, the control circuit providing a control signal that dynamically enables and disables the third input transistor based on, and for the duration of transitions of, the input signal.
2 more elements
A method for independently controlling input trip points of a logic input buffer comprising:
- receiving an input signal with the input buffer;
- generating a control signal based, in part, on the input signal;
- dynamically adjusting betas of selected ones of input transistors within the input buffer in accordance with the control signal, and
- wherein the betas are adjusted prior to, and for the duration of, transitions of the input signal.
1 more element
A logic buffer configured to receive and buffer an input signal, the buffer comprising:
- a first input transistor;
- a second input transistor coupled in series with the first input transistor;
- and
- a third input transistor coupled in parallel with the first or second input transistors,
- wherein the third input transistor is dynamically enabled prior to, and for the duration of, transitions of the input signal to provide a particular circuit characteristic.
2 more elements
Dependencies are inferred from the claim text.