Input buffer circuit

Abstract

An input buffer circuit includes a transition detecting unit for receiving an input signal, detecting a transition of the input signal, and outputting a detecting signal and a delayed input signal; a detecting signal summing unit for summing up the detecting signal and other detecting signals outputted from other transition detecting units, and outputting a plurality of summed signals; a buffer unit for transmitting the delayed input signal in accordance with the plurality of summed signals; a control signal generator for receiving one of the plurality of summed signals and a first control signal, and outputting a second control signal and a third control signal; and a write driver 204 for receiving the second and third control signals, and transmitting an output signal of the buffer unit to a cell by a trigger of the plurality of summed signals.

Dependencies are inferred from the claim text.