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US 6,147,511 AGranted
Overvoltage-tolerant interface for integrated circuits
AssigneeAltera Corporation
InventorsRakesh H. Patel, John E. Turner, Wilson Wong
Life of this patent
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Abstract
An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an "overvoltage condition. " For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.
Claims60
A circuit to implement an overvoltage-tolerant integrated circuit comprising:
- a pull-up device coupled between a first supply voltage and an I/O pad;
- and
- a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:
- a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;
- a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;
- a first clamping device coupled between the first supply voltage and a first node, not directly connected to the voltage bias node;
- a second clamping device coupled between the I/O pad and the first node;
- and
- a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state.
6 more elements
An integrated circuit comprising:
- a pull-up device coupled between a first supply voltage and an I/O pad;
- and
- a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:
- a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;
- a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;
- a first clamping device coupled between the first supply voltage and a first node;
- a second clamping device coupled between the I/O pad and the first node;
- a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state;
- and
- a voltage clamp device coupled to clamp the voltage bias node to about a voltage level at the I/O pad.
7 more elements
A circuit to implement an overvoltage-tolerant integrated circuit comprising:
- a pull-up device coupled between a first supply voltage and an I/O pad;
- and
- a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:
- a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;
- a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;
- and;
- a third bias device to couple the voltage bias node to a control electrode of the pull-up device whenever the pull-up device is in a nonconducting state.
4 more elements
An intergrated circuit comprising:
- a pull-up device coupled between a first supply voltage and an I/O pad;
- a predriver to drive the pull-up device;
- and
- an isolation device between the predriver and the control electrode of the pull-up device, wherein the isolation device is a pass transistor having a control electrode coupled to the first supply voltage;
- and
- a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:
- a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;
- a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;
- a first clamping device coupled between the first supply voltage and a first node;
- a second clamping device coupled between the I/O pad and the first node;
- and
- a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state.
9 more elements
An integrated circuit comprising:
- a pull-up device coupled between a first supply voltage and an I/O pad;
- a first pass device coupled between the I/O pad and the control electrode of the pull-up device, wherein a control electrode of the first pass device is coupled to the first supply voltage;
- and
- a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:
- a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;
- a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;
- a first clamping device coupled between the first supply voltage and a first node;
- a second clamping device coupled between the I/O pad and the first node;
- and
- a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state.
7 more elements
A circuit to implement an overvoltage-tolerant integrated circuit comprising:
- a pull-up device coupled between a first supply voltage and an I/O pad;
- a predriver to drive the pull-up device;
- and
- an isolation device between the predriver and the control electrode of the pull-up device, wherein the isolation device is a pass transistor having a control electrode coupled to the first supply voltage, and
- a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising:
- a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;
- and
- a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage, wherein the first bias device and the second bias device have a first gate oxide thickness that is thicker than a second gate oxide thickness of transistors used to implement the predriver.
5 more elements
A circuit to implement an overvoltage-tolerant integrated circuit comprising:
- a pull-up device coupled between a first supply voltage and an I/O pad;
- a predriver to drive a control electrode of the pull-up device with a pull-up signal;
- and
- a body bias generator, having a voltage bias node coupled to a first body electrode of the pull-up device, comprising:
- a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;
- a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;
- and
- a third bias device, coupled between the voltage bias node and the control electrode of the pull-up device, wherein a control electrode of the third bias device is coupled to an inverted version of the pull-up signal.
5 more elements
Dependencies are inferred from the claim text.