Integrated circuit for handling buffer contention and method thereof

An integrated circuit comprising:

• buffer circuitry for providing an output signal, the buffer circuitry comprising a tri-stateable buffer;
• a first terminal for receiving the output signal coupled to the buffer circuitry;
• a contention detection circuit coupled to the buffer circuitry wherein the contention detection circuit provides a contention tri-state control signal to the buffer circuitry, the contention tri-state control signal having a first logic value and a second logic value, and wherein the tri-stateable buffer is tri-stated when the buffer circuitry receives the contention tri-state control signal having the first logic value and wherein the buffer circuitry receives the contention tri-state control signal having the first logic value when the first terminal provides power to the buffer circuitry and the contention detection circuit;
• and
• internal circuitry coupled to the first terminal, wherein the internal circuitry provides a tri-state control signal to the buffer circuitry.

An integrated circuit comprising:

• buffer circuitry for providing an output signal, the buffer circuitry comprising a tri-stateable buffer and a level shifting circuit;
• a first terminal for receiving the output signal coupled to the buffer circuitry;
• and
• a contention detection circuit coupled to the buffer circuitry, wherein the contention detection circuit provides a contention tri-state control signal to the buffer circuitry, the contention tri-state control signal having a first logic value and a second logic value, and wherein the tri-stateable buffer is tri-stated when the buffer circuitry receives the contention tri-state control signal having the first logic value, and wherein the buffer circuitry receives the contention tri-state control signal having the first logic value when the first terminal provides power to the buffer circuitry and the contention detection circuit,
• wherein the level shifting circuit is coupled to the contention detection circuit and receives the contention tri-state control signal from the contention detection circuit.

A method for handling buffer contention, comprising the steps of:

• providing an integrated circuit, the integrated circuit having buffer circuitry formed therein, the buffer circuitry comprising a tri-stateable buffer;
• providing a contention tri-state control signal to the buffer circuitry, the contention tri-state control signal having a first logic value and a second logic value, wherein the tri-stateable buffer is tri-stated when the buffer circuitry receives the contention tri-state control signal having the first logic value;
• detecting that a potential buffer contention condition exists, said step of detecting comprising the step of detecting a predetermined voltage differential between a first power supply voltage and a second power supply voltage;
• and
• tri-stating the tri-stateable buffer when the potential buffer contention condition exists, wherein the buffer circuitry receives the contention tri-state control signal having the first logic value when the potential buffer contention condition exists.

A method for handling buffer contention, comprising the steps of:

• providing an integrated circuit, the integrated circuit having buffer circuitry and a contention detection circuit, the contention detection circuit having a first terminal and a second terminal and the buffer circuitry comprising a tri-stateable buffer;
• providing a contention tri-state control signal to the buffer circuitry, the contention tri-state control signal having a first logic value and a second logic value, wherein the tri-stateable buffer is tri-stated when the buffer circuitry receives the contention tri-state control signal having the first logic value;
• providing a first power supply voltage to the first terminal;
• providing a second power supply voltage to the second terminal;
• detecting a predetermined voltage differential between the first power supply voltage and the second power supply voltage;
• and
• tri-stating the tri-stateable buffer when the predetermined voltage differential is detected, wherein the buffer circuitry receives the contention tri-state control signal having the first logic value from the contention detection circuit when the predetermined voltage differential is detected.