Power consumption control mechanism and method therefor

A method of controlling power consumption of a logic device comprising the steps of:

• sending a completion signal from a first logic unit in said logic device to a second logic unit in said logic device in response to said first logic unit evaluating a first logic signal output from said second logic unit to a logic input of said first logic unit;
• generating first and second temperature-controlled p-type metal oxide semiconductor (PMOS) back bias signals, wherein said first and second PMOS back bias signals are controlled in response to a temperature of said first and second logic units, respectively, and wherein said first PMOS back bias signal is applied to a PMOS back bias input of said first logic unit and said second PMOS back bias signal is supplied to a PMOS back bias input of said second logic unit;
• and
• generating first and second temperature-controlled n-type metal oxide semiconductor (NMOS) back bias signals, wherein said first and second NMOS back bias signals are controlled in response to a temperature of said first and second logic units, respectively, and wherein said first NMOS back bias signal is applied to a NMOS back bias input of said first logic unit and said second NMOS back bias signal is supplied to a NMOS back bias input of said second logic unit.

A method of controlling power consumption of a logic device comprising the steps of

• sending a completion signal from a first logic unit in said logic device to a second logic unit in said logic device in response to said first logic unit evaluating a first logic signal output from said second logic unit to a logic input of said first logic unit, said second logic unit outputting a second logic signal in response to said completing signal;
• generating first and second temperature-controlled p-type metal oxide semiconductor (PMOS) back bias signals, wherein said first and second PMOS back bias signals are controlled in response to a temperature of said first and second logic units, respectively, in wherein said first PMOS back bias signal is applied to a PMOS back bias input of said first logic unit and said second PMOS back bias signal supplied to a PMOS back bias input of said second logic unit;
• and
• generating first and second temperature-controlled n-type metal oxide semiconductor (NMOS) back bias signals, wherein said first and second NMOS back bias signals are controlled in response to said temperature of said first and second logic units, respectively, and wherein said first NMOS back bias signal is applied to a NMOS back bias input of said first logic unit and said second NMOS back bias signal supplied to a NMOS back bias input of said second logic unit, and wherein a rate of said first and second logic signals and said completion signal is determined in response to said first and second PMOS and said first and second NMOS back bias signals.