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US 6,147,413 AGranted
Mask repattern process
AssigneeMicron Technology, Inc.
InventorWarren M. Farnworth
Life of this patent
Estimating the term…
Abstract
The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.
Claims11
A semiconductor device, said device comprising:
- a semiconductor substrate including at least one circuit thereon connected to a bond pad, a first passivation layer thereon covering said at least one circuit and having an aperture therethrough located at the bond pad, metallization forming at least one solder wettable conductive trace having a portion thereof connected to the bond pad and located on a portion of the first passivation layer, an insulative second passivation layer covering said metallization and portions of the first passivation layer, said second insulative passivation layer including at least one sloped-wall via therethrough located over a portion of said metallization, and a solder material located in the at least one sloped-wall via in said second insulative passivation layer, said solder material directly contacting a portion of said at least one solder wettable conductive trace, said at least one sloped wall via including:
- a portion of the metallization forming said at least one solder wettable conductive trace directly contacting said solder material and in electrical communication with integrated circuitry carried by said semiconductor substrate connected to said at least one circuit.
A semiconductor device, said device comprising:
- a semiconductor substrate including at least one circuit thereon connected to a bond pad, a first passivation layer thereon covering said at least one circuit and having an aperture therethrough located at the bond pad, metallization forming at least one solder wettable conductive trace having a portion thereof connected to the bond pad and located on a portion of the first passivation layer, an insulative stress absorbing second passivation layer covering said metallization and portions of the first passivation layer, said second passivation layer including at least one sloped-wall via therethrough located over a portion of said metallization, and a solder material located in the at least one sloped-wall via in said second passivation layer, said solder material directly contacting a portion of said at least one solder wettable conductive trace, said at least one sloped wall via including:
- a portion of the metallization forming said at least one solder wettable conductive trace directly contacting said solder material and in electrical communication with integrated circuitry carried by said semiconductor substrate connected to said at least one circuit.
A semiconductor device, said device comprising:
- a semiconductor substrate including at least one circuit thereon connected to a bond pad, a first passivation layer thereon covering said at least one circuit and having an aperture therethrough located at the bond pad, metallization forming at least one solder wettable conductive trace having a portion thereof connected to the bond pad and located on a portion of the first passivation layer, a non-conductive second passivation layer covering said metallization and portions of the first passivation layer, said second passivation layer including at least one sloped-wall via therethrough located over a portion of said metallization, and a solder material located in the at least one sloped-wall via in said second passivation layer, said solder material directly contacting a portion of said at least one solder wettable conductive trace, said at least one sloped wall via including:
- a portion of the metallization forming said at least one solder wettable conductive trace directly contacting said solder material and in electrical communication with integrated circuitry carried by said semiconductor substrate connected to said at least one circuit.
A semiconductor device, said device comprising:
- a semiconductor substrate including at least one circuit thereon connected to a bond pad, a first passivation layer thereon covering said at least one circuit and having an aperture therethrough located at the bond pad, metallization forming at least one solder wettable conductive trace having a portion thereof connected to the bond pad and located on a portion of the first passivation layer, a second passivation layer without conductive particles therein covering said metallization and portions of the first passivation layer, said second passivation layer including at least one sloped-wall via therethrough located over a portion of said metallization, and a solder material located in the at least one sloped-wall via in said second passivation layer, said solder material directly contacting a portion of said at least one solder wettable conductive trace, said at least one sloped wall via including:
- a portion of the metallization forming said at least one solder wettable conductive trace directly contacting said solder material and in electrical communication with integrated circuitry carried by said semiconductor substrate connected to said at least one circuit.
A semiconductor device, said device comprising:
- a semiconductor substrate including at least one circuit thereon connected to a bond pad, a first passivation layer thereon covering said at least one circuit and having an aperture therethrough located at the bond pad, metallization forming at least one solder wettable conductive trace having a portion thereof connected to the bond pad and located on a portion of the first passivation layer, a second passivation layer without particles therein covering said metallization and portions of the first passivation layer, said second passivation layer including at least one sloped-wall via therethrough located over a portion of said metallization, and a solder material located in the at least one sloped-wall via in said second passivation layer, said solder material directly contacting a portion of said at least one solder wettable conductive trace, said at least one sloped wall via including:
- a portion of the metallization forming said at least one solder wettable conductive trace directly contacting said solder material and in electrical communication with integrated circuitry carried by said semiconductor substrate connected to said at least one circuit.
A semiconductor device, said device comprising:
- a semiconductor substrate including at least one circuit thereon connected to a bond pad, a first passivation layer thereon covering said at least one circuit and having an aperture therethrough located at the bond pad, metallization forming at least one solder wettable conductive trace having a portion thereof connected to the bond pad and located on a portion of the first passivation layer, a second passivation layer having no particles therein covering said metallization and portions of the first passivation layer, said second passivation layer including at least one sloped-wall via therethrough located over a portion of said metallization, and a solder material located in the at least one sloped-wall via in said second passivation layer, said solder material directly contacting a portion of said at least one solder wettable conductive trace, said at least one sloped wall via including:
- a portion of the metallization forming said at least one solder wettable conductive trace directly contacting said solder material and in electrical communication with integrated circuitry carried by said semiconductor substrate connected to said at least one circuit.
A semiconductor device, said device comprising:
- a semiconductor substrate including at least one circuit thereon connected to a bond pad, a first passivation layer thereon covering said at least one circuit and having an aperture therethrough located at the bond pad, metallization forming at least one solder wettable conductive trace having a portion thereof connected to the bond pad and located on a portion of the first passivation layer, a second passivation layer having no conductive particles therein covering said metallization and portions of the first passivation layer, said second passivation layer including at least one sloped-wall via therethrough located over a portion of said metallization, and a solder material located in the at least one sloped-wall via in said second passivation layer, said solder material directly contacting a portion of said at least one solder wettable conductive trace, said at least one sloped wall via including:
- a portion of the metallization forming said at least one solder wettable conductive trace directly contacting said solder material and in electrical communication with integrated circuitry carried by said semiconductor substrate connected to said at least one circuit.
Dependencies are inferred from the claim text.