US 6,147,393 A · Isolated multi-chip devices

Abstract

A semiconductor device structure in which a power semiconductor device is used as the substrate for the structure. Initially, a first metallization layer is formed on the power semiconductor device. Then, a dielectric passivation layer is formed over the first metallization layer, the dielectric passivation layer having apertures through which the first metallization layer may be accessed. A polymer passivation layer is then formed on the dielectric passivation layer, the polymer passivation layer also having apertures through which the first metallization layer and the dielectric passivation layer may be accessed. A second metallization layer is then formed on the polymer passivation layer and at least one electronic component is attached to the polymer passivation layer or the second metallization layer. The polymer passivation layer provides galvanic isolation between the power semiconductor device and the electronic component.

Claims18

Dependent claims

A semiconductor device structure, comprising:

a power semiconductor device which is used as a substrate for the structure;
a first metallization layer formed on the power semiconductor device;
a first passivation layer formed on the first metallization layer;
a second passivation layer formed on the first passivation layer, the second passivation layer comprising a polymer;
a second metallization layer formed on the second passivation layer;
and
at least one electronic component soldered to the second metallization layer, wherein the second passivation layer provides galvanic isolation between the power semiconductor device and the electronic component and wherein the second passivation layer is capable of withstanding temperatures greater than about 100.degree. C.

4 more elements

Dependencies are inferred from the claim text.

Isolated multi-chip devices

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Isolated multi-chip devices

Life of this patent

Abstract

Claims18