Floating gate non-volatile memory cell with low erasing voltage and having different potential barriers
AssigneeSGS-Thomson Microelectronics S.A.
InventorPaolo Cappelletti
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Abstract
A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
Claims35
A non-volatile memory cell on a semiconductor substrate comprising:
- at least one floating gate transistor comprising
- a source region,
- a drain region,
- a channel region separating said source and drain regions,
- a floating gate region and a control terminal coupled thereto, and
- a gate oxide layer over said channel region for isolating said floating gate region from the substrate,
- said floating gate region having a focused electric field and developing a first potential barrier between the semiconductor substrate and the gate oxide layer, and said floating gate region developing a second different potential barrier between the floating gate region and the gate oxide layer.
A non-volatile memory comprising:
- a semiconductor substrate;
- and
- a plurality of memory cells each comprising at least one floating gate transistor on the semiconductor substrate, said floating gate transistor comprising a gate oxide layer on said substrate and a floating gate region thereon having a focused electric field and developing a first potential barrier between the semiconductor substrate and the gate oxide layer and for developing a second different potential barrier between the floating gate region and the gate oxide layer.
A non-volatile memory cell on a semiconductor substrate comprising:
- at least one floating gate transistor comprising
- a source region,
- a drain region,
- a channel region separating said source and drain regions,
- a floating gate region and a control terminal coupled thereto, and
- a gate oxide layer over said channel region for isolating said floating gate region from the substrate, said gate oxide layer further comprising a first layer of material of a first type adjacent to the surface of the semiconductor substrate and a second layer of material of a second type whose electron affinity lies intermediate to those of the first layer and the floating gate region,
- said floating gate region having a focused electric field and developing a first potential barrier between the semiconductor substrate and the gate oxide layer, and said floating gate region developing a second different potential barrier between the floating gate region and the gate oxide layer.
Dependencies are inferred from the claim text.