US 6,147,377 A · Fully recessed semiconductor device

Abstract

A fully recessed device structure and method for low power applications comprises a trenched floating gate and a trenched control gate formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography for low power applications. The trenched floating gate is electrically isolated from the trenched control gate by an inter-gate dielectric layer formed inside the trench and on a top surface of the trenched floating gate. The trenched control gate is formed on a top surface of the inter-gate dielectric layer and preferably, has a top surface which is substantially planar with a top surface of the semiconductor substrate. The fully recessed structure further comprises a buried source region, a buried drain region and a channel region. The buried source region and the buried drain region are formed in the well junction region and are laterally separated by the trench. The buried source region and the buried drain region have a depth slightly less than the depth of the trench. In one embodiment, the buried source and buried drain region have asymmetrical depths that are both approximately less than the depth of the trench. In one embodiment of the present invention, sidewall dopings are formed in the substrate to shield the trenched control gate from the buried source and buried drain regions.

Claims14

Dependent claims

A semiconductor transistor for low power applications formed in a semiconductor substrate having a top surface comprising:

a well junction region of one conductivity type formed in the semiconductor substrate;
a trench formed in the well junction region intermediate a source region and a drain region within the semiconductor substrate and having substantially vertical sidewalls and a bottom surface, the bottom surface being disposed at a first depth;
said source region being formed of opposite conductivity type in the well junction region having a lower boundary disposed at a second depth, the second depth being less than the first depth of the trench relative to the top surface of the semiconductor substrate;
said drain region being formed of the opposite conductivity type in the well junction region spaced from the source region and having a lower boundary disposed at a third depth, the third depth being less than the first depth of the trench relative to the top surface of the semiconductor substrate;
a channel region formed beneath the bottom surface of the trench;
a trench-to-gate insulating layer formed on the sidewalls and on the bottom surface inside the trench;
a trenched floating gate electrode formed inside the trench and on the trench-to-gate insulating layer to a depth below the top surface;
an inter-gate dielectric layer formed inside the trench on the trenched floating gate electrode;
and
a trenched control gate electrode formed inside the trench and on the inter-gate dielectric layer.

7 more elements

A semiconductor transistor for low power applications formed in a semiconductor substrate having a top surface comprising:

a well junction region of one conductivity type formed in the semiconductor substrate;
a trench formed in the well junction region and intermediate the buried source region and the buried drain region and having substantially vertical sidewalls and a bottom surface at a first depth;
a buried source region of opposite conductivity type formed in the well junction region having a lower boundary disposed at a second depth which is less than the first depth of the trench relative to the top surface of the semiconductor substrate;
a buried drain region of opposite conductivity type formed in the well junction region spaced from the buried source region and having a lower boundary disposed at a third depth which is less than the first depth of the trench relative to the top surface of the semiconductor substrate;
a channel region formed beneath the bottom surface of the trench;
a trench-to-gate insulating layer formed on the vertical sidewalls and on the bottom surface inside the trench;
a trenched floating gate electrode formed inside the trench and on the trench-to-gate insulating layer;
the trenched floating gate electrode having a top surface which is disposed at approximately one half the first depth of trench;
an inter-gate dielectric layer formed inside the trench and on the trenched floating gate electrode;
and
a trenched control gate electrode formed inside the trench and on the intergate dielectric layer;
the trenched control gate electrode having a top surface which is substantially planar to the top surface of the semiconductor substrate.

9 more elements

Dependencies are inferred from the claim text.

Fully recessed semiconductor device

Life of this patent

Fully recessed semiconductor device

Life of this patent

Abstract

Claims14