Focal plane readout unit cell background suppression circuit and method

A background suppression circuit suitable for use with an integrated focal plane readout unit cell, comprising:

• an integrating capacitor arranged to receive a first current representing a photocurrent for a predetermined integration period and to store the charge developed from said first current, said capacitor having a maximum charge capacity,
• a field-effect transistor (FET) having a current circuit connected to said capacitor and a control input connected to receive a skimming pulse at least once per integration period, said FET operating as a controlled current source which reduces the quantity of charge stored on said capacitor by a controlled amount when said skimming pulse is received, and
• a pulse generation circuit arranged to generate at least one of said skimming pulses per integration period, said at least one skimming pulse having a duration substantially shorter than said integration period and an amplitude sufficient to drive said FET into its strong inversion mode, said capacitor, FET and pulse generation circuit integrated together on a common substrate,
• said reduction of stored charge enabling an increased quantity of photocurrent to be integrated during said integration period when said photocurrent would otherwise exceed the charge capacity of said capacitor.

A focal plane readout unit cell with a background suppression circuit, comprising:

• a photodetector interface circuit connected to receive a photocurrent at an input and to produce a first current at an output,
• an integrating capacitor arranged to receive said first current for a predetermined integration period and to store the charge developed from said first current, said capacitor having a maximum charge capacity,
• a field-effect transistor (FET) having a current circuit connected to said capacitor and a control input connected to receive a skimming pulse, said FET operating as a controlled current source which reduces the quantity of charge stored on said capacitor by a controlled amount when said skimming pulse is received, and
• a pulse generation circuit arranged to generate at least one of said skimming pulses per integration period, said at least one skimming pulse having a duration substantially shorter than said integration period and an amplitude sufficient to drive said FET into its strong inversion mode, said photodetector interface circuit, integrating capacitor, FET and pulse generation circuit integrated together on a common substrate,
• said reduction of stored charge enabling an increased quantity of photocurrent to be integrated during said integration period when said photocurrent would otherwise exceed the charge capacity of said integrating capacitor.

An integrated focal plane array with improved background suppression, comprising:

• a plurality of focal plane readout unit cells arranged into a row and column array, each unit cell comprising:
• a photodetector interface circuit connected to receive a photocurrent at an input and to produce a first current at an output,
• an integrating capacitor arranged to receive said first current for a predetermined integration period and to store the charge developed from said first current, said capacitor having a maximum charge capacity, and
• a field-effect transistor (FET) having a current circuit connected to said capacitor and a control input connected to receive a skimming pulse, said FET operating as a controlled current source which reduces the quantity of charge stored on said capacitor by a controlled amount when said skimming pulse is received;
• clock generation circuitry arranged to generate at least one of said skimming pulses per integration period for each of said FETs in said array, each skimming pulse having a duration substantially shorter than said integration period and an amplitude sufficient to drive the receiving FET into its strong inversion mode, and
• a plurality of column multiplexers connected to respective columns of said unit cells for assembling the charges from said array of unit cells into a video frame, said unit cells, clock generation circuitry and column multiplexers integrated together on a common substrate.