Method of making a semiconductor device comprising copper interconnects with reduced in-line copper diffusion
AssigneeAdvanced Micro Devices, Inc.
InventorsMinh Van Ngo, Takeshi Nogami
Life of this patent
Estimating the term…
Loading patent…
AssigneeAdvanced Micro Devices, Inc.
InventorsMinh Van Ngo, Takeshi Nogami
Estimating the term…
Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a high strength ammonia plasma to ion bombard the exposed inter line silicon oxide with nitrogen atoms, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.
A method of manufacturing a semiconductor device, the method comprising:
Dependencies are inferred from the claim text.