US 6,146,978 AGranted

Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance

AssigneeAdvanced Micro Devices, Inc.

InventorsMark W. Michael, Robert Dawson, H. Jim Fulford, Jr., Mark I. Gardner, Frederick N. Hause, Bradley T. Moore, Derick J. Wristers

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Abstract

An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode such as an insulated gate field effect transistor (IGFET) source/drain region surface. The etch barrier provides controlled etching to allow for overlap of the interlevel interconnect onto the isolation barrier without increased parasitic capacitance relative to conventional contact misalignments. Furthermore, allaying concerns of overlapping allows for increased utilization of source/drain region surface area by the interlevel interconnect. Furthermore, the etch barrier allows the interlevel interconnect to strap electrodes of a plurality of circuit devices while exhibiting nominal if any substrate to interlevel interconnect leakage currents.

Claims8

Dependent claims

An integrated circuit having an interconnect structure comprising:

a substrate;
a circuit device having a channel region and a source/drain disposed in the substrate, wherein the channel region and the source/drain intersect at a boundary parallel to a width dimension of the source/drain;
an electrical isolation barrier disposed adjacent to the circuit device source/drain;
an electrical isolation layer disposed over the substrate and having an opening of at least substantially the width dimension of the source/drain, wherein the opening extends over at least a portion of the isolation barrier;
an etch barrier disposed between the isolation layer and the substrate, the etch barrier having an opening coinciding with the isolation layer opening and separated from the substrate;
and
an interlevel interconnect disposed in the openings in the isolation layer and the etch barrier and coupled to the circuit device source/drain, wherein the interlevel interconnect includes a surface co-planar with a surface of the isolation layer opposite the substrate.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/073,639Filed 6 May 1998
Granted: 14 Nov 2000
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/0186
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10W 20/0698
Of conductive parts of the interconnections: local interconnections
H10W 20/081
Of dielectric parts thereof: by forming openings in the dielectric parts