Minimizing transistor size in integrated circuits

A method of fabricating at least a pair of local interconnects with one interconnect on each side of a gate of a field effect transistor (FET) in an integrated circuit on a semiconductor substrate comprising the steps of:

• forming on a semiconductor substrate a thick insulating layer;
• forming at least a pair of spaced apart openings in the insulating layer adjacent the semiconductor substrate;
• forming a source in one of said openings and a drain in the other of the openings;
• filling each of said openings with a conductive material to form local interconnects to the source and drain;
• removing a portion of said insulating layer to form a gate opening between the local interconnects;
• forming a gate oxide on the semiconductor substrate in the gate opening;
• and
• forming a gate on the gate oxide in gate opening between the local interconnects wherein insulating spacers are formed from a conformal insulating layer in the gate opening on each of the local interconnects.

A method of fabricating at least a pair of local interconnects with one interconnect on each side of a gate of a field effect transistor (FET) in an integrated circuit on a semiconductor substrate comprising the steps of:

• forming on a semiconductor substrate a thick insulating layer;
• forming at least a pair of spaced apart openings in the insulating layer adjacent the semiconductor substrate;
• forming a source in one of said openings and a drain in the other of the openings;
• filling each of said openings with a conductive material to form local interconnects to the source and drain;
• removing a portion of said insulating layer to form a gate opening between the local interconnects;
• forming a gate oxide on the semiconductor substrate in the gate opening;
• and
• forming a gate on the gate oxide in gate opening between the local interconnects wherein the source and drain are formed by implanting impurities in the pair of openings in the insulating layer.

A method of fabricating at least a pair of local interconnects with one interconnect on each side of a gate of a field effect transistor (FET) in an integrated circuit on a semiconductor substrate comprising the steps of:

• forming on a semiconductor substrate a thick insulating layer;
• forming at least a pair of spaced apart openings in the insulating layer adjacent the semiconductor substrate;
• forming a source in one of said openings and a drain in the other of the openings;
• filling each of said openings with a conductive material to form local interconnects to the source and drain;
• removing a portion of said insulating layer to form a gate opening between the local interconnects;
• forming a gate oxide on the semiconductor substrate in the gate opening;
• and
• forming a gate on the gate oxide in gate opening between the local interconnects wherein the portion of insulating material is removed by using a masking material with an opening in the masking material positioned between said pair of local interconnects.

A method of fabricating at least a pair of local interconnects with one interconnect on each side of a gate of a field effect transistor (FET) in an integrated circuit on a semiconductor substrate comprising the steps of:

• forming on a semiconductor substrate a thick insulating layer;
• forming at least a pair of spaced apart openings in the insulating layer adjacent the semiconductor substrate;
• forming a source in one of said openings and a drain in the other of the openings;
• filling each of said openings with a conductive material to form local interconnects to the source and drain;
• removing a portion of said insulating layer to form a gate opening between the local interconnects;
• forming a gate oxide on the semiconductor substrate in the gate opening;
• and
• forming a gate on the gate oxide in gate opening between the local interconnects wherein a conductive layer is formed on the walls of the local interconnect openings to line the opening and the remainder of the local interconnect opening is filled with another conductive material.

A method of fabricating at least a pair of local interconnects with one interconnect on each side of a gate of a field effect transistor (FET) in an integrated circuit on a semiconductor substrate comprising the steps of:

• forming on a semiconductor substrate a thick insulating layer;
• forming at least a pair of spaced apart openings in the insulating layer adjacent the semiconductor substrate;
• forming a source in one of said openings and a drain in the other of the openings;
• filling each of said openings with a conductive material to form local interconnects to the source and drain;
• removing a portion of said insulating layer to form a gate opening between the local interconnects;
• forming a gate oxide on the semiconductor substrate in the gate opening;
• and
• forming a gate on the gate oxide in gate opening between the local interconnects wherein a barrier layer is formed on the walls of the local interconnect openings to line the opening and the remainder of the local interconnect opening is filled with a conductive material.

A method of fabricating at least a pair of local interconnects with one interconnect on each side of a gate of a field effect transistor (FET) in an integrated circuit on a semiconductor substrate comprising the steps of:

• forming on a semiconductor substrate a thick insulating layer;
• forming at least a pair of spaced apart openings in the insulating layer adjacent the semiconductor substrate;
• forming a source in one of said openings and a drain in the other of the openings;
• filling each of said openings with a conductive material to form local interconnects to the source and drain;
• removing a portion of said insulating layer to form a gate opening between the local interconnects;
• forming a gate oxide on the semiconductor substrate in the gate opening;
• and
• forming a gate on the gate oxide in gate opening between the local interconnects wherein an insulating etch stop layer is formed on semiconductor substrate before forming the thick insulating layer.

A method of fabricating at least a pair of local interconnects with one interconnect on each side of a gate of a field effect transistor (FET) in an integrated circuit on a semiconductor substrate comprising the steps of:

• forming on a semiconductor substrate a thick insulating layer;
• forming at least a pair of spaced apart openings in the insulating layer adjacent the semiconductor substrate;
• forming a source in one of said openings and a drain in the other of the openings;
• filling each of said openings with a conductive material to form local interconnects to the source and drain;
• removing a portion of said insulating layer to form a gate opening between the local interconnects;
• forming a gate oxide on the semiconductor substrate in the gate opening;
• and
• forming a gate on the gate oxide in gate opening between the local interconnects wherein the gate is selected from the group of polysilicon, refractory metal and metal.

In a method of fabricating, in an integrated circuit on a semiconductor substrate, a field effect transistor (FET) having a source, drain and gate and with one interconnect on each side of a gate of the FET comprising the steps of:

• forming on a semiconductor substrate a thick insulating layer;
• forming a pair of spaced apart openings in the insulating layer adjacent the semiconductor substrate, each opening being the size of a minimum lithographic feature;
• forming a source in one of said openings and a drain in the other of the openings;
• filling each of said openings with a conductive material to form local interconnects to the source and drain;
• removing a portion of said insulating layer to form a gate opening of a minimum lithographic feature between the local interconnects;
• forming a gate oxide on the semiconductor substrate in the gate opening;
• and
• forming a gate on the gate oxide in gate opening between the local interconnects, whereby the size of the FET transistor is three minimum lithographic features wherein openings in the insulating material is positioned over active regions in the semiconductor substrate and the opening in masking material extends to or beyond the active region on the sides of the opening removed from the local interconnects.