Method of fabricating a dynamic random access memory device

A method of fabricating a capacitor of a dynamic random access memory, transistor comprising:

• providing a substrate with at least one active region and at least one field oxide area formed therein and adjacent to the active region;
• forming a gate oxide layer on the active region;
• depositing a first conductive layer on the active region;
• forming a cap oxide layer on the first conductive layer;
• patterning the cap oxide layer, the first conductive layer and gate oxide layer to form a gate electrode structure of a MOS transistor;
• forming sidewall spacers on sidewalls of the gate electrode structure;
• performing a self-aligned ion implantation process in the substrate to form a plurality of source/drain regions;
• forming a mask layer on the substrate, the mask covering at least one of the source/drain regions and a part of the cap oxide of the gate electrode structure;
• after said forming a mask layer, selectively forming an insulating layer on an exposed part of the gate electrode structure and on the substrate using liquid-phase deposition;
• removing the mask layer, exposing the one of the source/drain regions, thereby forming a contact window over the one of the source/drain regions, wherein said forming a mask layer, said selectively forming and said removing prevents the insulating layer from forming within the contact window, and wherein said forming a mask layer, said selectively forming and said removing are performed without etching the cap insulating layer;
• forming a second patterned conductive layer on the substrate, the second patterned conductive layer covering only a part of the insulating layer and being electrically coupled to the one of the source/drain regions to form a lower electrode of the capacitor;
• forming a dielectric layer on the second conductive layer;
• and
• forming a third conductive layer on the dielectric layer to form an upper electrode of the capacitor.

A method of fabricating a capacitor of a dynamic random access memory, the method comprising:

• providing a substrate with at least one active region, and at least one field oxide area formed thereon;
• forming a gate oxide layer on the active region;
• depositing a polysilicon layer on the active region and elsewhere on the substrate;
• forming a cap oxide layer on the polysilicon layer;
• patterning the cap oxide layer, polysilicon layer and gate oxide layer to form a gate electrode structure of a MOS transistor;
• forming sidewall spacers on sidewalls of the gate electrode structure;
• performing a self-aligned ion implantation process in the substrate to form a plurality of source/drain regions;
• before forming an oxide layer, forming a photoresist layer on the substrate, covering one of the source/drain regions and a part of the cap oxide layer of the gate electrode structure;
• selectively forming the oxide layer over an exposed portion of the gate electrode structure and over the substrate surface;
• removing the photoresist layer, thereby forming a contact window over the one of the source/drain regions, wherein said forming a photoresist layer, said selectively forming and said removing prevents the oxide layer from forming within the contact window, and wherein said forming a photoresist layer, said selectively forming and said removing are performed without etching the cap oxide layer;
• forming and patterning a first polysilicon layer on the substrate, the first polysilicon layer being electrically coupled to the one of the source/drain regions to form a lower electrode of the capacitor;
• forming a dielectric layer on the first polysilicon layer;
• and
• forming a second polysilicon layer on the dielectric layer to form a lower electrode of the capacitor.