Lateral gate, vertical drift region transistor

A method of fabricating a lateral gate, vertical drift region transistor comprising the steps of:

• providing a semiconductor substrate having a first surface and an opposite surface and positioning a first current terminal on the opposite surface;
• forming a doped structure of a first conductivity type with a buried region positioned therein wherein the buried region is formed of a second conductivity type that is opposite to the first conductivity type and that is opposite to the conductivity type of the remainder of the doped structure and positioning the doped structure on the first surface of the substrate, forming the doped structure with a surface parallel to and spaced from the first surface of the substrate, positioning the buried region in the doped structure so as to define a drift region in the doped structure extending from and generally perpendicular to the first surface of the substrate, and further positioning the buried region in the doped structure so as to define a doped region in communication with the drift region and adjacent the surface of the doped structure;
• positioning a second current terminal on the doped structure in communication with the doped region;
• implanting material in the doped region to form an implant region adjacent the surface of the doped structure in communication with the second current terminal and the buried region;
• positioning an insulating layer on the surface of the doped structure overlying the doped region and the implant region;
• and
• positioning a control terminal on the insulating layer so as to define an inversion region in the implant region, extending the inversion region laterally adjacent the control terminal and in communication with the drift region and the second current terminal.