US 6,146,908 A · Method of manufacturing a test circuit on a silicon wafer

Abstract

The invention relates to a method of manufacturing, on a silicon wafer, a plurality of integrated circuits and at least one test circuit, comprising steps of insulation of the silicon wafer by means of a reticle disposed in an exposure chamber provided with a diaphragm which allows to hide the non useful parts of the reticle. According to the invention, the method comprises an insulation (exposure) step performed by means of a reticle (130) comprising an insulation mask region (132) for integrated circuits together with at least one insulation mask region (133, 134, 135) for a test circuit. The insulation step includes one or more insulation steps during which the insulation mask region for test circuit is hidden by the diaphragm, and at least one insulation step during which the insulation mask region for test circuit is uncovered by the diaphragm, while all or part of the insulation mask for integrated circuit is hidden by the diaphragm.

Claims19

Dependent claims

A method of manufacturing, on a silicon wafer, a plurality of integrated circuits and at least one test circuit, comprising:

insulation of the silicon wafer through a reticle disposed in an exposure chamber and provided with a diaphragm which allows a portion of the reticle to be hidden, wherein at least one insulation step performed through the reticle exposes at least part of an insulation mask portion for integrated circuits together with an insulation mask portion for a test circuit, the insulation mask portion for the test circuit disposed so as to be able to be hidden by the diaphragm without hiding the insulation mask portion for the integrated circuits.

A method of producing integrated circuits and test structures on a wafer, comprising:

providing a reticle having an area larger than an exposure area employing in exposing regions of the wafer, the reticle including
a first portion having an area equal to the exposure area and including a plurality of patterns for an integrated circuit, and
a second portion smaller than the exposure area and including at least one pattern for a test structure;
providing a diaphragm capable of selectively
masking the second portion of the reticle while exposing only the first portion, or
masking part of the first portion of the reticle while exposing the second portion;
exposing a plurality of circuit regions on the wafer through the reticle with the diaphragm masking the second portion of the reticle and exposing only the first portion of the reticle to form the plurality of patterns for the integrated circuit on each of the plurality of circuit regions;
and
exposing at least one test region on the wafer through the reticle with the diaphragm masking part of the first portion of the reticle and exposing the second portion to form the test structure on the at least one test region.

6 more elements

Dependencies are inferred from the claim text.

Method of manufacturing a test circuit on a silicon wafer

Life of this patent

Method of manufacturing a test circuit on a silicon wafer

Life of this patent

Abstract

Claims19