Integrated circuits with copper metallization for interconnections
AssigneeInfineon Technologies North America Corp.
InventorMark D. Hoinkis
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Abstract
An improved fill of high aspect ratio trenches by copper is obtained by first sputtering a thin nucleating film of copper deposited by physical vapor deposition, then depositing a thin seed layer of copper by chemical vapor deposition, and then completing the fill by electroplating. Stress migration of the fill is improved if the copper deposition is preceded by the deposition by CVD of a layer of titanium nitride either alone or preceded and/or followed by the deposition of tantalum by an ionized PVD source.
Claims16
A method for the deposition of copper to fill a trench in the surface of a semiconductive device and provide an interconnection pattern for an integrated circuit comprising the steps of:
- first depositing over the walls of the trench to be filled a barrier layer by depositing in turn a tantalum-rich layer of at least 50 Angstroms thick, a titanium nitride layer of at least 50 Angstroms thick and a tantalum-rich layer of at least 50 Angstroms thick;
- and
- then filling the trench with copper.
A method of filling a trench having an aspect ratio greater than six at the surface of a semiconductive device comprising the steps of:
- forming a barrier layer over the walls of the trench,
- depositing by physical vapor deposition over the barrier layer a flash layer of copper less than 1000 Angstroms thick;
- depositing by chemical vapor deposition over the flash copper layer a seed copper layer of less than 1000 Angstroms thick;
- and
- filling the trench with copper by electroplating.
Dependencies are inferred from the claim text.