Method and apparatus for performing multiple types of multiplication including signed and unsigned multiplication
AssigneeAdvanced Micro Devices, Inc.
InventorStuart F. Oberman
Life of this patent
Estimating the term…
Loading patent…
AssigneeAdvanced Micro Devices, Inc.
InventorStuart F. Oberman
Estimating the term…
A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and may include a partial product generator, a selection logic unit, and an adder. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. The multiplier is also configured to receive a first control signal indicative of whether signed or unsigned multiplication is to be performed and a second control signal indicative of whether vector multiplication is to be performed. The multiplier is configured to calculate an effective sign for the multiplier and multiplicand operands based upon each operand's most significant bit and the control signal. The effective signs may then be used by the partial product generation unit and the selection logic to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, the adder is configured to sum them and output the results, which may be signed or unsigned. When a vector multiplication is performed, the multiplier is configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.
A multiplier capable of performing both signed and unsigned multiplication comprising:
A multiplier capable of performing both signed and unsigned multiplication comprising:
A method for operating a multiplier within a microprocessor comprising:
Dependencies are inferred from the claim text.