Non-volatile inverter latch
AssigneeCypress Semiconductor Corporation
InventorKenelm G. D. Murray
Life of this patent
Estimating the term…
Abstract
A two-transistor, zero DC power, non-volatile inverter latch that can be made using floating-gate or SONOS technology to provide a consistent and/or reliable logic high and/or logic low output level. The inventive cell is useful for holding option settings in any custom integrated circuit or, more specifically, for holding configuration information (e.g., ASIC, PLD or FPGA interconnect data; configuration data for such ICs or for a clock/oscillator circuit or a microcontroller, etc.). The inventive cell outputs the data state immediately on power-up without any need for recall sequencing. The benefit of the invention comes from the potential for a very small cell which, in many applications, can substitute for non-volatile RAM.
Claims31
A nonvolatile memory cell, comprising:
- an input;
- a first variable threshold transistor configured to receive said input and a first voltage;
- a second variable threshold transistor configured to receive said input and a second voltage;
- and
- an output node coupled to said first variable threshold transistor and said second variable threshold transistor.
A nonvolatile memory cell, comprising:
- a P-channel variable threshold transistor configured to receive a first input and a first voltage;
- an N-channel variable threshold transistor configured to receive a second input and a second voltage;
- and
- an output node coupled to said N-channel variable threshold transistor and said P-channel variable threshold transistor.
A method of storing a logic and/or data level and/or state in a cell in an array, comprising the steps of:
- (A) applying an overvoltage to control gates of first and second variable threshold transistors in a plurality of cells in said array;
- and
- (B) at least one of the following steps:
- (i) applying a first operating voltage to a source/drain terminal of each of said first and second variable threshold transistors in cells selected for storing said logic and/or data level and/or state;
- and/or
- (ii) applying a second operating voltage to the source/drain terminal of each of said first and second variable threshold transistors in cells not selected for storing said logic and/or data level and/or state, said second operating voltage representing a logic level opposite that of the corresponding voltage for cells selected for storing said logic and/or data level and/or state.
Dependencies are inferred from the claim text.