Method and apparatus for implementing a serial memory architecture
AssigneeIntel Corporation
InventorsMichael W. Leddige, Bryce D. Horine
Life of this patent
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Abstract
A serial memory architecture. A memory subsystem includes a bus and a first memory module coupled to the bus. The first memory module has a first connector to receive bus signals from the bus and a second connector to output the bus signals. A second memory module has a first connector to receive the bus signals from the second connector of the first memory module. The bus signals are thereby routed through the memory modules in a serial manner. In one embodiment the memory modules include one or more 90.degree. routing paths between connectors and the devices of the memory modules. In one embodiment, trace lengths are matched.
Claims19
A memory system, comprising:
- a first memory module having a first electrical connector coupled to a bus, the first electrical connector to receive a set of signals, the set of signals to be serially routed through a first plurality of memory devices of the first memory module to a second electrical connector on the first memory module, wherein the first plurality of memory devices is connected in series between the first electrical connector and the second electrical connector on the first memory module, the second electrical connector coupled to a last memory device of the first plurality of memory devices connected in series of the first memory module;
- and
- a second memory module connected in series with the first memory module, wherein the second memory module has a first electrical connector coupled to the second electrical connector of the first memory module to receive the set of signals, the set of signals to be serially routed through a second plurality of memory devices of the second memory module to a second electrical connector on the second memory module, wherein the second plurality of memory devices is connected in series between the first electrical connector and the second electrical connector on the second memory module, the second electrical connector coupled to a last memory device of the second plurality of memory devices connected in series of the second memory module.
A computer system, comprising:
- a bus;
- a processor coupled to the bus;
- a memory controller coupled to the bus;
- a memory system, coupled to the memory controller having:
- a first memory module having a first electrical connector coupled to the bus, the first electrical connector to receive a set of signals, the set of signals to be serially routed through a first plurality of memory devices of the first memory module to a second electrical connector on the first memory module, wherein the first Plurality of memory devices is connected in series between the first electrical connector and the second electrical connector on the first memory module, the second electrical connector coupled to a last memory device of the first plurality of memory devices connected in series of the first memory module;
- and
- a second memory module connected in series with the first memory module, wherein the second memory module had a first electrical connector coupled to the second electrical connector of the first memory module to receive the set of signals, the set of signals to be serially routed through a second plurality of memory devices of the second memory module to a second electrical connector on the second memory module, wherein the second plurality of memory devices is connected in series between the first electrical connector and the second electrical connector on the second memory module, the second electrical connector coupled to a last memory device of the second plurality of memory devices connected in series of the second memory module.
A method of routing memory bus signals, the method comprising:
- routing the memory bus signals to a first electrical connector of a first memory module;
- serially routing the memory bus signals through one or more components of the first memory module;
- routing the memory bus signal to a second electrical connector of the first memory module;
- and
- serially routing the memory bus signals to a first electrical connector of a second memory module.
Dependencies are inferred from the claim text.