Data processing method, and data processor and printer using data processing method
AssigneeCanon Kabushiki Kaisha
InventorsShinichi Omo, Hiroshi Fukui, Akira Kuronuma, Takayuki Murata, Masahiko Umezawa
Life of this patent
Estimating the term…
Loading patent…
AssigneeCanon Kabushiki Kaisha
InventorsShinichi Omo, Hiroshi Fukui, Akira Kuronuma, Takayuki Murata, Masahiko Umezawa
Estimating the term…
A data processing method which efficiently performs data transfer by using a data bus with an appropriate access width corresponding to transfer data and a printer using the data processing method. In the printer, a CPU bus 70 having a 16-bit physical bus width, is shared by a CPU 21 and a DMAC 80. In a case where the CPU 21 accesses a memory via the CPU bus 70 with an 8-bit width, while the DMAC 80 accesses the memory via the CPU bus 70 with a 16-bit width, each time the DMAC 80 needs to access the memory, the DMAC 80 issues a DMA request signal to the CPU 21, requiring an exclusive access right for the CPU bus 70. In accordance with the request signal, the CPU 21 delivers the exclusive access right for the CPU bus 70 to the DMAC 80. Then the DMAC 80 controls memory access with the 16-bit width.
A data processing method for accessing a memory by a CPU and a DMA controller via a bus with an N-bit physical bus width, comprising:
A printer which accesses a memory by using a CPU an a DMA controller, comprising:
A data processing apparatus for accessing a memory by a CPU and a DMA controller via a bus with an N-bit physical bus width, comprising:
Dependencies are inferred from the claim text.