Apparatus for driving a flat panel display

An apparatus for driving a flat panel display, comprising:

• a shift register for sequentially shifting data input from the exterior in a synchronized manner;
• a plurality of latches for performing parallel processing of input data by latching the input data by using the signal output from said shift register as a synchronization signal, said plurality of latches allowing for a display in accordance with the output of data synchronized with a clock signal by inputting an output of a first latch stage into a second latch stare upon activation of a first enable signal, and inputting an output of the second latch stage into a 4-bit output stage upon activation of a second enable signal;
• an AND gate for outputting the signal output through said plurality of latches on a bit by bit basis;
• and
• an output driving circuit for enabling a display gradation processing by controlling the amount of currents in accordance with the signal output from said AND gate, said output driving circuit receiving a single supply voltage and including,
• an analog multiplexer for inputting a digitized signal through said AND gate and outputting a voltage corresponding to said digitized signal;
• an operational amplifier responsive to the signal output from said analog multiplexer for comparing the signal output from said analog multiplexer with a voltage applied from a power supply and adjusting the current gain of a transistor at a subsequent stage in accordance with a voltage difference from said comparison;
• a voltage divider connected between the power supply and said operational amplifier and between said operational amplifier and an output stage of said analog multiplexer;
• and
• a transistor for controlling an amount of electrons emitted from a cathode in accordance with a current gain applied at said operational amplifier and for applying the controlled amount of electrons to a display panel.

An apparatus for driving a flat panel display, comprising:

• a shift register for sequentially shifting data input from the exterior in a synchronized manner;
• a plurality of latches for performing parallel processing of input data by latching the input data by using the signal output from said shift register as a synchronization signal, said plurality of latches allowing for a display in accordance with the output of data synchronized with a clock signal by inputting an output of a first latch stage into a second latch stage upon activation of a first enable signal, and inputting an output of the second latch stage into a 4-bit output stage upon activation of a second enable signal;
• an AND gate for outputting the signal output through said plurality of latches on a bit by bit basis;
• and
• an output driving circuit for enabling a display gradation processing by controlling the amount of current in accordance with the signal output from said AND gate, said output driving circuit being supplied with a plurality of voltages corresponding to a display gradation processing and including,
• an analog multiplexer for selecting and outputting a corresponding voltage upon receiving a digitized signal through said AND gate;
• an operational amplifier for inputting and amplifying a voltage output from said analog multiplexer, and for applying the amplified voltage to a subsequent transistor;
• a transistor for driving a display panel in accordance with the voltage applied from said operational amplifier;
• and
• a resistor for maintaining a constant voltage between said operational amplifier and a ground of said transistor, a first end of said resistor being commonly connected to an emitter end of said transistor and said operational amplifier, and a second end of said resistor being connected to the ground.