Variable length code processor with encoding and/or decoding
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHisakazu Sato
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHisakazu Sato
Estimating the term…
A variable length code processor is obtained which can perform encoding or decoding process in a plurality of variable length encoding standards. A sequence control section (5) has two control registers (VL.sub.-- MODE and VL.sub.-- CNT). A CPU (2) sets the desired value to the control register (VL.sub.-- MODE) to select a processing content to be performed by a VLC processor (4). A local memory (7) is realized by a 4K-byte RAM to store retrieval tables used in decoding or encoding process. The sequence control section (5) controls a second DCT buffer section (11), an address generating section (12), a DCT generating section (14), VLC generating section (14), a shifter section (15), a VLC buffer section (16), and a VLC pack section (17), so that the process indicated by the control register (VL.sub.-- MODE) is executable.
A variable length code processor comprising:
Dependencies are inferred from the claim text.