Circuit for measuring signal delays of asynchronous register inputs

Abstract

A circuit measures a signal propagation delay through a series of memory elements on a programmable logic device. In one embodiment, a number of latches are configured in series. Each latch is initialized to store a logic zero. The first latch is then clock-enabled so that the output of the latch rises to a logic one. The logic one from the first latch clock-enables the second latch in the series so that the output of the second latch rises to a logic one, which in turn enables the next latch in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each latch to change in response to a clock-enable signal. Consequently, the delay through the series of latches provides a measure of the time required for one of the latches to respond to a clock-enable signal. In another embodiment, the latches are arranged in a loop so that the sequence of latches forms a ring oscillator, the period of which provides an indication of the time required for the latches to respond to clock-enable signals. Other embodiments include sequences of flip-flops arranged as delay elements or ring oscillators. Those embodiments provide means for measuring the time required for flip-flops to respond to preset or clear signals.

Dependencies are inferred from the claim text.