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US 6,144,250 AGranted
Error amplifier reference circuit
AssigneeLinear Technology Corporation
InventorsRichard T. Owen, Dennis P. O'Neill
Life of this patent
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AssigneeLinear Technology Corporation
InventorsRichard T. Owen, Dennis P. O'Neill
Estimating the term…
An error amplifier circuit is provided having a pair of current mirror transistors driven by a pair of current sources, where one of the current mirror transistors operates at a lower current density than the other, and further having a resistor in an emitter circuit of the transistor operating at the lower current density and a summing node in the emitter circuit between the emitter of the one transistor and the resistor. A feedback circuit including a second resistor and a base-emitter circuit of a third transistor is in series between a feedback node coupled to the base of the feedback transistor and the summing node, such that a current from the feedback circuit is summed with the current conducted by the emitter of the one transistor. The error amplifier is balanced when the voltage at the feedback node is equal to a predetermined voltage, which can have substantially zero temperature coefficient at a voltage as low as one bandgap voltage. A resistive divider may be coupled to the feedback node, such that the error amplifier is balanced when the voltage at a node of the resistive divider is at a predetermined voltage greater than the bandgap voltage. The error amplifier may be used, among other applications, as a control circuit for a low dropout voltage regulator which is capable of producing a regulated output voltage, having nominally zero temperature drift over a wide operating range, substantially equal to or greater than the bandgap voltage.
An error amplifier circuit for use in a control circuit, said error amplifier circuit comprising:
An error amplifier circuit, comprising:
A method for producing an error signal at an output of an error amplifier, the error amplifier including first and second current mirror transistors conducting currents provided by respective first and second current sources, the current mirror transistors operating at different current densities, and including a first resistive impedance in an emitter circuit of at least one of the current mirror transistors and a summing node in the emitter circuit located between the emitter of the one current mirror transistor and the first resistive impedance, the first resistive impedance conducting a first current provided by said one current mirror transistor, the method comprising:
Dependencies are inferred from the claim text.