Method and circuit arrangement for reducing offset voltage of a signal
AssigneeNokia Mobile Phones Ltd.
InventorRisto Vaisanen
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AssigneeNokia Mobile Phones Ltd.
InventorRisto Vaisanen
Estimating the term…
The invention relates to a method and a circuit arrangement for reducing the offset voltage of a signal. The invention can be applied preferably in direct conversion receivers which are used, for example, in mobile stations used in digital time-division cellular systems. According to the invention, the direct voltage component of a signal is separated by a capacitor (C1) and the offset voltage is reduced by connecting a second signal (S2) to the output (P2) of the capacitor, the amplitude of this signal being determined on the basis of a first signal (S1) preceding the capacitor (C1). The second signal (S2) is formed preferably by high-pass filtering said first signal (S1) and by summing a reference voltage (Vref) to the high-pass filtered signal (S3). By using the solution according to the invention, it is possible to reduce the offset voltage also when there are no breaks in the received baseband signal.
A method for reducing offset voltage of a first signal having a direct voltage component, comprising:
A circuit arrangement for reducing the offset voltage of a first signal, comprising:
In a direct conversion receiver for reducing the offset voltage of a baseband signal, a method for reducing offset voltage of a first signal having a direct voltage component, comprising:
In a receiver of a mobile station, a method for reducing offset voltage of a first signal having a direct voltage component, comprising:
In a digital, time-division mobile communication system, a method for reducing offset voltage, of a first signal having a direct voltage component, in a telephone of said system, the method comprising:
Dependencies are inferred from the claim text.