US 6,144,238 A · Integrated power-on-reset circuit

Abstract

A circuit and a method are disclosed which offer a solution for integrating a power-on-reset circuit that is realizable in a small space, consumes very little power, and works for practically any rate of rise of the power supply. These goals have been achieved by detecting, in a first section of the circuit, when the supply voltage reaches the threshold voltage V.sub.TP of a p-channel transistor, and activates power-on-reset by forcing that signal to logical zero (active). This first section detects next when the supply voltage reaches 2V.sub.TP and signals to a second section of the circuit to start charging a capacitor. The charging rate of the capacitor is controlled in such a way that its voltage lags behind the supply voltage, so that if the rise of the supply voltage is very fast, the duration T.sub.D of power-on-reset is long enough to insure complete resetting of the circuits it serves, such as digital memory elements, digital registers etc. A third section of the circuit monitors the voltage of the capacitor and when this capacitor voltage has reached a certain predetermined percentage of the supply voltage, this third section terminates power-on-reset by switching that signal to logical one (inactive).

Claims21

Dependent claims

An integrated circuit generating a self-timed power-on-reset signal, comprising:

a first level detector monitoring the rise of its own supply voltage and making said supply voltage available at an output only when said supply voltage ranges in value from a transistor threshold to two times said transistor threshold;
a timing block using said output of said first level detector and charging a capacitor after said supply voltage at said output has reached two times said transistor threshold and then dropped to a voltage near ground;
and
a second level detector with a node OUT, said second level detector, using a voltage at said capacitor as input, switching said node OUT from a low voltage, equal to a power-on-reset, to said supply voltage, equal to a NOT power-on-reset, when said capacitor has exceeded a predefined voltage V.sub.H, where said voltage V.sub.H equals the sum of about half said supply voltage and the threshold voltage of an n-channel transistor.

1 more element

An integrated circuit generating a self-timed power-on-reset signal, comprising:

a supply voltage;
a reference potential;
a first level detector connected between said supply voltage and said reference potential, said first level detector monitoring the rise of said supply voltage and providing a voltage signal at a node n3;
a timing block connected between said supply voltage and said reference potential and to said node n3, said timing block charging a capacitor and providing said capacitor's voltage signal at a node n4;
and
a second level detector connected between said supply voltage and said reference potential and to said node n4, said second level detector resetting a power-on-reset signal at a node OUT, when said capacitor has exceeded a predefined voltage V.sub.H, where said voltage V.sub.H equals the sum of about half said supply voltage and the threshold voltage of an n-channel transistor.

3 more elements

Dependencies are inferred from the claim text.

Integrated power-on-reset circuit

Life of this patent

Integrated power-on-reset circuit

Life of this patent

Abstract

Claims21