Generalized push-pull cascode logic technique
AssigneeCompaq Computer Corporation
InventorsMark D. Matson, Sridhar Samudrala, Robert J. Dupcak
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Abstract
A method and apparatus are presented for efficient implementation of logic and arithmetic functions that generate sets of mutually exclusive output signals. Such a logic family includes a network of NMOS transistors that implements a desired logic function. Coupled to that network is a minimal number of PMOS devices for providing logic level restoration and for compensating for any voltage drops due to the NMOS transistors. With such a structure, the speed, area and power consumption characteristics of logic functions are improved.
Claims42
An apparatus for generating a set of mutually exclusive output signals, comprising:
- a network of NMOS devices that implement a desired logic function, said network generating a number of output signals that are asserted in a mutually exclusive manner;
- and
- a configuration of PMOS devices, each of said PMOS devices being associated with one of said output signals for raising ones of said output signals to logic high levels, said configuration comprising a number of PMOS devices, said number being equivalent to one less than the number of said output signals, each of said PMOS devices comprising a gate terminal coupled to each of said output signals except the output signal to which it is associated.
A computer system, comprising:
- a central processing unit connected to a memory system by a system bus;
- an I/O system, connected to the system bus by a bus interface device;
- and
- a logic function, implemented within said central processing unit, comprising a network of NMOS devices said network generating a number of output signals that are asserted in a mutually exclusive manner, said logic function further comprising a configuration of a number of PMOS devices, each of said PMOS devices being associated with one of said output signals for raising ones of said output signals to logic high levels, said number being equivalent to one less than the number of said output signals, each of said PMOS devices comprising a gate terminal coupled to each of said output signals except the output signal to which it is associated.
A method for implementing a logic circuit to generate a set of mutually exclusive output signals, comprising the steps of:
- designing said logic circuit to implement a desired logic function that generates said mutually exclusive output signals in response to input signals conveyed to said logic circuit, said logic circuit designed using NMOS devices;
- associating a number of PMOS devices with each of said mutually exclusive output signals, said number of PMOS devices being one less than the number of said mutually exclusive output signals;
- and
- connecting each gate terminal of said PMOS devices that are coupled to a given one of said mutually exclusive output signals, to a different one of the other mutually exclusive output signals.
An apparatus comprising:
- a means for asserting ones of a group of output signals in a mutually exclusive manner, said means implemented by a network of NMOS transistor devices;
- and
- a means for raising de-asserted ones of said output signals to de-asserted logic levels, said means implemented by a configuration comprising a number of PMOS devices, said number being equivalent to one less than the number of said output signals, each of said PMOS devices comprising a gate terminal coupled to each of said output signals except the output signal to which it is associated.
Dependencies are inferred from the claim text.