Programmable integrated circuit having metal plate capacitors that provide local switching energy
AssigneeXilinx, Inc.
InventorAustin Lesea
Life of this patent
Estimating the term…
Abstract
Certain digital logic elements within the core of a field programmable integrated gate array (FPGA) require relatively large spikes of supply current when they switch. Local integrated metal plate bypass capacitors are provided in the core of the FPGA near the digital logic elements. The local integrated bypass capacitors provide the digital logic elements with a substantial portion of the required spikes of supply current. The magnitude of supply current spikes drawn over resistive and/or inductive power leads from the edges of the FPGA is therefore reduced and associated drops in supply voltage at the core are reduced.
Claims15
An integrated circuit, comprising:
- a capacitor comprising a first planar metal plate and a second planar metal plate, the first planar metal plate having a lateral boundary, the second planar metal plate having a lateral boundary, the first planar metal plate extending in a first plane, the second planar metal plate extending in a second plane, the first plane being parallel to the second plane;
- a power bus extending in a third plane, the third plane being substantially parallel to the first plane and to the second plane, the power bus being coupled to the second planar metal plate of the capacitor;
- a first logic block comprising a first digital logic element;
- and
- a second logic block comprising a second digital logic element, the second digital logic element having an output lead coupled to an input lead of the first digital logic element, the second logic block having a lateral boundary, the lateral boundaries of the first and second planar metal plates being disposed in the lateral dimension within the lateral boundary of the second logic block, during a switching period of a voltage on the output lead from a first digital logic level to a second digital logic level a peak current ICAPpeak flows from the second planar metal plate of the capacitor and to the second digital logic element, during the switching period a peak current ICCpeak flows from the power bus and to the second digital logic element, ICCpeak being smaller than ICAPpeak.
A method of fabricating an integrated circuit, comprising:
- fabricating a digital logic element in a core of the integrated circuit, the digital logic element comprising a P channel pullup transistor, the P channel pullup transistor having a gate length of less than 0.20 microns, a source of the P channel pullup transistor being a supply voltage terminal of the digital logic element;
- fabricating a local parallel plate bypass capacitor in the core of the integrated circuit, the bypass capacitor having a first metal plate and a second metal plate, the second metal plate being coupled to the supply voltage terminal, one of the first and second metal plates being formed of a first layer of metal whereas the other of the first and second metal plates is formed of a second layer of metal, the first and second metal plates being separated by less than 0.75 microns, each of the first and second metal plates occupying an area of at least 750 square microns;
- and
- fabricating a power supply bus that is formed of a third layer of metal, the power supply bus being coupled to the second metal plate.
Dependencies are inferred from the claim text.