FPGA Architecture using multiplexers that incorporate a logic gate

Abstract

A structure in which blocks of random access memory, or RAM, are integrated with FPGA configurable logic blocks. Routing lines which access configurable logic blocks also access address, data, and control lines in the RAM blocks. Thus, the logic blocks of the FPGA can use these routing lines to access portions of RAM. According to the invention, a decoder which enables dedicated RAM is configurable to respond in many different ways to decoder input signals. The decoder can be programmed to be enabled by any combination of decoder input signals and can be programmed to ignore any number of decoder input signals. The ability to ignore input signals is important in FPGAs because it saves having to route a disabling signal to an unused decoder input terminal. The decoder can also be programmed to be disabled regardless of decoder input signals. The decoder can be programmed to treat a set of input signals as an address, and can invert or not invert the address.

Dependencies are inferred from the claim text.