System and method for isolation of varying-power backed memory controller inputs

A low power memory fresh isolation system, comprising:

• a) a first low power indicator input signal having an active state;
• b) a second low power indicator input signal having an active state;
• c) a digital logic block having an output and having a first input connected to said first low power indicator signal and a second input connected to said second low power indicator signal;
• d) a DSP circuit having data output signals and a first low power indicator signal output;
• e) a power monitor circuit having a second low power indicator signal output;
• f) a memory data refresh controller circuit having data inputs connected to said DSP data outputs, having an input connected to said second low power indicator signal output, and having data outputs;
• wherein in response to the event when said first and second low power indicator input signals each enter their respective active state, said memory data refresh controller circuit data ouputs become disabled.

A method of isolating data output from a memory refresh device from a memory circuit input during periods of low power, comprising the steps of:

• a) providing a data refresh isolation circuit;
• b) providing a memory data refresh circuit;
• c) providing a DSP circuit;
• d) inputting DSP data from said DSP circuit to said data refresh isolation circuit;
• e) providing a plurality of low power indicator signals, each having a respective active state, to said data refresh isolation circuit;
• f) disabling DSP data output from said data refresh isolation circuit in response to the event when said plurality of low popwer indicator signals all enter their respective active state, indicating a low power condition has occurred.

An arrangement of isolating data output from a memory refresh device from a memory circuit input during periods of low power, comprising:

• means for isolating a data fresh;
• refresh means for refreshing memory data;
• DSP means for processing digital signals;
• means for passing data from the DSP means to the refresh means;
• signaling means for outputting a plurality of lower power indicator signals, each having a respective active state, to the refresh means;
• means, responsive to each of the plurality of lower power indicator signals entering its active state, for disabling data from passing from the DSP means to the refresh means.