High speed analog compensated input buffer
AssigneeIntel Corporation
InventorsJeffrey E. Smith, Varin Udompanyanan
Life of this patent
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Abstract
An analog process/voltage/temperature (PVT) compensated buffer includes a differential amplifier providing a first output signal indicative of a difference between an input signal and a reference signal. The input signal is compatible with a first type of logic. An active gain stage is coupled to translate the first output signal to a second output signal. The second output signal is compatible with a second type of logic. The differential amplifier and the active gain stage are coupled to receive a process/voltage/temperature (PVT) compensation signal. In one embodiment, the first type of logic is Gunning Transceiver Logic (GTL) and the second type of logic is complementary metal oxide semiconductor (CMOS) logic.
Claims19
An apparatus comprising:
- a differential amplifier providing a first output signal indicative of a difference between an input signal and a reference signal, wherein the input signal is compatible with a first type of logic;
- and
- an active gain stage coupled to receive the first output signal, wherein the active gain stage translates the first output signal to a second output signal compatible with a second type of logic, wherein the differential amplifier and the active gain stage are coupled to receive a process/voltage/temperature (PVT) compensation signal;
- wherein the PVT compensation signal comprises:
- (i) a Gunning Transceiver Logic (GTL) transistor bias compensation signal,
- (ii) a complementary metal oxide semiconductor (CMOS) logic bias compensation signal, and
- (iii) a plurality of low pass filters.
An apparatus comprising:
- a differential amplifier comparing an input signal and a reference signal to provide a first output signal, wherein the input signal is compatible with a first type of logic;
- and
- an active gain stage, wherein the active gain stage translates the first output signal to a second output signal compatible with a second type of logic;
- wherein the differential amplifier comprises:
- (i) an active current mirror load,
- (ii) a first current source biased by a process/voltage/temperature (PVT) compensation signal, wherein the first current source provides a first current substantially independent of PVT variations,
- wherein the PVT compensation signal comprises:
- (a) a Gunning Transceiver Logic (GTL) transistor bias compensation signal,
- (b) a complementary metal oxide semiconductor (CMOS) logic bias compensation signal, and
- (c) a plurality of low pass filters,
- (iii) a first transistor coupled to the first current source and a first node of the active current mirror load, the first transistor receiving the input signal, and
- (iv) a second transistor coupled to the first current source and a second node of the active current mirror load, the second transistor biased by the reference signal, wherein the first output signal is provided from one of the first and second nodes,
- wherein the active gain stage comprises:
- (i) a second current source biased by the PVT bias compensation signal, and
- (ii) a third transistor coupled to the second current source at an output node, the third transistor coupled to receive the first output signal, wherein the second output signal is provided at the output node.
Dependencies are inferred from the claim text.