US 6,144,214 AGranted

Method and apparatus for use in IDDQ integrated circuit testing

AssigneeUniversity of South Florida

InventorStephan P. Athan

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Abstract

A built in current sensor circuit (BICS) for use in integrated circuit testing utilizing the Quiescent Power Supply testing technique comprised of a detecting transistor, an s-ram cell and a buffer cell electrically coupled in a cascaded configuration to perform a comparator function, a reference source comprised of a current generating transistor and a voltage level setting transistor, and an active output load comprised of a single p-MOSFET sized to draw a unique amount of current when a respective circuit under test is determined to be defective., whereby the additional current drawn by the active output load is readily observable on the bias line by an external standard off-the-shelf current monitor. The built in current sensor circuit thereby alleviates the excessive use of area overhead in deep submicron integrated circuits and the need for separately propagating a defect signal to an output pin.

Claims4

Dependent claims

A built in current sensor circuit for use in testing integrated circuits for defects by sensing current increases caused by the defects, said built in current sensor circuit comprising in combination:

detecting means for detecting circuit flow through the integrated circuit and providing a representative signal therefor, said detecting means comprising a detecting transistor that produces the representative signal;
reference source means for providing a reference threshold signal, said reference source means being electrically coupled relative to said detecting means;
comparator means for comparing the reference threshold signal to the representative signal, said comparator means being electrically coupled to said detecting means and electrically coupled to said reference source means;
said reference source means comprising a current generating transistor electrically coupled to a voltage level setting transistor, whereby the voltage level setting transistor is electrically coupled to said comparator means, said detecting transistor having process parameters that match the process parameters of said voltage level setting transistor;
and an active output load electrically coupled to said comparator means, said active output load being sized to draw a disproportionately larger current when turned on than the current caused by the defect in the integrated circuit,
whereby said comparator means turns on said active output load when said representative signal is determined to be larger than said reference threshold signal and the current draw of the active output load is resultantly sensed indicating that the integrated circuit is defective.

3 more elements

A method for testing integrated its for defects utilizing quiescent power supply current testing comprising the steps of:

providing an integrated circuit having input terminals and output terminals, the integrated circuit being electrically coupled to a bias line;
providing a built in current sensor circuit electrically coupled to the output terminal of the integrated circuit and electrically coupled to the bias line;
biasing up the integrated circuit and the built in current sensor circuit by applying power to the bias line;
applying predetermined test pattern signals to the input terminals of the integrated circuit;
detecting the total curent flowing through the integrated circuit and producing a representative signal therefor;
providing a predetermined reference threshold signal;
comparing the representative signal to a predetermined reference threshold signal;
turning on an active output load so to enable an output current to be drawn when the representative signal is compared to the reference threshold signal and a defect is determined, wherein the active output load is sized to draw a specific output current that is disproportionately larger than the current due to the defect, and when the unique amount of current drawn by the active output load is identified with the popular integrated circuit being tested by the built in current sensor circuit;
monitoring the bias line to detect any disproportionate increase in current and determining the amount of increase over the current of the integrated circuit and built in current sensor circuit at steady state to identify the particular integrated circuit that is defective;
and
the step of biasing up said integrated circuit and said built in current sensor circuit by applying power to the bias line comprising the step of applying a timing signal to said built in current sensor circuit so as to intermittently bias up the built in current sensor circuit and periodically perform comparisons of the representative signal to the predetermined reference threshold signal.

8 more elements

Dependencies are inferred from the claim text.