Metallization layer

An integrated circuit, comprising:

• a number of semiconductor devices formed on a semiconductor substrate;
• a metallization layer that selectively interconnects the semiconductor devices to form a circuit;
• and
• wherein the metallization layer comprises non-alloy copper that is formed by electro-deposition of metal ions by applying a bipolar modulated voltage to selectively patterned first and second layers of material on the semiconductor substrate with different surface potentials, so as to form metal lines and fill contact vias in a single deposition step.

An integrated circuit, comprising:

• a layer of semiconductor material;
• a number of semiconductor devices formed in the semiconductor substrate;
• an insulator layer formed outwardly from the layer of semiconductor material;
• a first patterned layer of material with a first innate surface potential formed outwardly from the insulator layer;
• a number of contact vias formed through the insulator layer and the first patterned layer to provide for contact to the semiconductor devices;
• a second patterned layer of material with a second innate surface potential formed outwardly from the first patterned layer and lining the contact vias;
• and
• a non-alloy, copper metallization layer formed outwardly from the second patterned layer.

An integrated circuit, comprising:

• a layer of semiconductor material;
• a number of semiconductor devices formed in the semiconductor substrate;
• an insulator layer formed outwardly from the layer of semiconductor material;
• a first patterned layer of material with a first innate surface potential formed outwardly from the insulator layer;
• a number of contact vias formed through the insulator layer and the first patterned layer to provide for contact to the semiconductor devices;
• a second patterned layer of material with a second innate surface potential formed outwardly from the first patterned layer and lining the contact vias;
• a metallization layer formed outwardly from the second patterned layer;
• and
• wherein the metallization layer comprises nickel deposited on the second patterned layer by electro-deposition.

An integrated circuit, comprising:

• a layer of semiconductor material;
• a number of semiconductor devices formed in the semiconductor substrate;
• an insulator layer formed outwardly from the layer of semiconductor material;
• a first patterned layer of material with a first innate surface potential formed outwardly from the insulator layer;
• a number of contact vias formed through the insulator layer and the first patterned layer to provide for contact to the semiconductor devices;
• a second patterned layer of material with a second innate surface potential formed outwardly from the first patterned layer and lining the contact vias;
• a metallization layer formed outwardly from the second patterned layer;
• and
• wherein the metallization layer comprises palladium deposited on the second patterned layer by electro-deposition.