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AssigneeInternational Business Machines Corporation
InventorsLouis Lu-Chen Hsu, Chang-Ming Hsieh, Lyndon Ronald Logan, Jack Allan Mandelman, Seiki Ogura
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A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.
A field effect transistor isolated by shallow trench isolation devoid of local oxidation of silicon (LOCOS) isolation, said shallow trench isolation having a channel width between first and second shallow trenches at first and second shallow trench edges and a gate which extends across said channel width between said first and second shallow trenches, said gate having a first length at said shallow trench edges and a second length less than said first length between said shallow trench edges, said first length and said second length being related such that a threshold voltage, V.sub.t, at said shallow trench edges is substantially equal to V.sub.t between said shallow trench edges.
Dependencies are inferred from the claim text.