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US 6,144,077 AGranted
Semiconductor device comprising a bipolar transistor
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorYukio Maki
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Abstract
A semiconductor device is provided in its base region with an emitter region consisting of a p-type first impurity layer having a first impurity concentration peak at a first depth and a p-type second impurity layer having an impurity concentration peak at a second depth, and ohmic contact is provided in the p-type second impurity layer. Due to this structure, the operability of an SRAM memory cell defining an emitter region of a bipolar transistor by a source/drain region of a MOS transistor can be improved.
Claims4
A semiconductor device comprising:
- a first conductivity type semiconductor substrate;
- a second conductivity type collector region formed up to a position of a first depth from a major surface of said semiconductor substrate;
- a first conductivity type base region formed up to a position of a second depth, being smaller than said first depth, from said major surface of said semiconductor substrate;
- and
- an emitter region provided with a first impurity layer having a second conductivity type impurity concentration peak on a position of a third depth, being smaller than said second depth, from said major surface of said semiconductor substrate and a second impurity layer having a second conductivity type impurity concentration peak on a position between said second and third depths and being formed to be enclosed with said first impurity layer, wherein said base region is formed by a source/drain region of a MOS transistor.
2 more elements
A semiconductor device comprising:
- a first conductivity type semiconductor substrate;
- a second conductivity type collector region formed up to a position of a first depth from a major surface of said semiconductor substrate;
- a first conductivity type base region formed up to a position of a second depth, being smaller than said first depth, from said major surface of said semiconductor substrate;
- and
- an emitter region provided with a first impurity layer having a second conductivity type impurity concentration peak on a position of a third depth, being smaller than said second depth, from said major surface of said semiconductor substrate and a second impurity layer having a second conductivity type impurity concentration peak on a position between said second and third depths and being formed to be enclosed with said first impurity layer, further comprising a first conductivity type intrinsic base region being in contact with said second impurity layer and so formed as to extend in the depth direction for reaching said collector region.
2 more elements
Dependencies are inferred from the claim text.