US 6,144,076 A · Well formation For CMOS devices integrated circuit structures

Abstract

A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region. The dopant concentration level peak of the dopants forming the buried P well in the substrate will be located below the dopant concentration level peak of the N well a minimum distance sufficient to inhibit reduction of the effective depth of the N well, and a maximum distance not exceeding the maximum distance which will still provide enhanced latchup protection to one or more transistors formed in the CMOS region.

Claims21

Dependent claims

An integrated circuit structure formed on a semiconductor substrate with enhanced protection against latchup in a CMOS region of said integrated circuit structure by provision of a buried P well in said CMOS region spaced within a particular vertical distance range below an N well and a first P well in said CMOS region, said CMOS region comprising;

a) an N well in said substrate extending down from the surface of said substrate;
b) a first P well extending down from said surface of said substrate adjacent said N well;
c) a buried P well formed in said substrate [at least] beneath said N well and said first P well, wherein the depth of the peak dopant concentration in said buried P well is;
(i) spaced from the peak dopant concentration of said N well a minimum distance of at least about 0.7 .mu.m which will not introduce an amount of P type dopant into the region of the substrate where the N well has been or will be formed sufficient to reduce the effective depth of said N well;
and
(ii) spaced a maximum distance from said peak dopant concentration of said N well not exceeding about 1.1 .mu.m, wherein the resistance path from said buried P well to said substrate surface will not be too high to provide enhanced latchup protection to one or more transistors formed in said CMOS region;
and
d) an isolation region extending down from said surface of said substrate and separating at least a portion of said N well from said first P well, wherein:
i) the minimum depth of said isolation region substrate is at least equal to the depth of one or more source/drain regions formed in said N well and/or said first P well of said CMOS region to provide punch through protection for said source/drain regions;
and
ii) the minimum width of said isolation region between said N well and said first P well, at said surface of said substrate, is further that width:
1) sufficient to permit formation of said isolation region in said substrate to said minimum depth;
and
2) sufficient to permit formation of a P-N junction beneath said isolation region capable of functioning as a channel stop between said source/drain regions formed in said respective wells.

11 more elements

A CMOS region formed in an integrated circuit structure on a semiconductor substrate with enhanced protection against latchup by provision of a buried P well in said CMOS region spaced within a particular vertical distance beneath an N well and a first P well in said CMOS region, said CMOS region comprising;

a) an N well in said substrate extending down from the surface of said substrate;
b) a first P well extending down from said surface of said substrate adjacent said N well;
c) a buried P well formed in said substrate beneath said N well and said first P well, wherein the depth of the peak dopant concentration in said buried P well is:
(i) spaced from the peak dopant concentration of said N well a minimum distance of at least about 0.7 .mu.m, to thereby not introduce an amount of P type dopant into the region of the substrate where the N well has been or will be formed sufficient to reduce the effective depth of said N well;
and
(ii) spaced a maximum distance not exceeding about 1.1 .mu.m from said peak dopant concentration of said N well. whereby the resistance path from said buried P well up to the surface of said substrate will not be too high to provide enhanced latchup protection to one or more transistors formed in said CMOS region;
and
d) an isolation region extending down from said surface of said substrate and separating at least a portion of said N well from said first P well, wherein:
i) the depth of said isolation region substrate ranges from about 200 nm to about 500 nm to provide punch through protection for source/drain regions of one or more transistors formed in said CMOS region;
and
ii) the minimum width of said isolation region between said N well and said first P well, at said surface of said substrate, is at least about 0.6 .mu.m to thereby:
1) permit formation of said isolation region in said substrate to said minimum depth;
and
2) permit formation of a P-N junction beneath said isolation region capable of functioning as a channel stop between said source/drain regions formed respectively in said N well and said first P well.

11 more elements

An integrated circuit structure formed on a semiconductor substrate with enhanced protection against latchup in a CMOS region of said integrated circuit structure by provision of a builed P well in said CMOS region spaced within a particular vertical distance range below an N well and a first P well in said CMOS region, said CMOS region comprising;

a) an N well in said substrate extending down from the surface of said substrate;
b) a first P well extending down from said surface of said substrate adjacent said N well to a depth approximating that of said N well;
c) a buried P well formed in said substrate beneath said N well and said first P well, wherein the depth of the peak dopant concentration in said buried P well is:
(i) spaced from the peak dopant concentration of said N well a minimum distance of at least about 0.7 .mu.m, to thereby not introduce an amount of P type dopant into the region of the substrate where the N well has been or will be formed sufficient to reduce the effective depth of said N well;
and
(ii) spaced a maximum distance of not greater than 1.1 .mu.m from said peak dopant concentration of said N well, whereby the resistance path from said buried P well to said substrate surface will not be too high to provide enhanced latchup protection to one or more transistors formed in said CMOS region;
and
d) an isolation region extending down from said surface of said substrate and separating at least a portion of said N well from said first P well, wherein:
i) the minimum depth of said isolation region substrate is at least equal to the depth of one or more source/drain regions formed in said N well and/or said first P well of said CMOS region to thereby provide punch through protection for said source/drain regions;
and
ii) the minimum width of said isolation region between said N well and said first P well, at said surface of said substrate, is further that width:
1) sufficient to permit formation of said isolation region in said substrate to said minimum depth;
and
2) sufficient to permit formation of a P-N junction beneath said isolation region capable of functioning as a channel stop between said source/drain regions formed in said respective wells.

11 more elements

Dependencies are inferred from the claim text.

Well formation For CMOS devices integrated circuit structures

Life of this patent

Well formation For CMOS devices integrated circuit structures

Life of this patent

Abstract

Claims21