Protection of the logic well of a component including an integrated MOS power transistor
AssigneeSGS-Thomson Microelectronics S.A.
InventorIsabelle Claverie
Life of this patent
Estimating the term…
Abstract
The present invention relates to a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components being formed in at least one well of the second type of conductivity and on the upper surface side of the substrate. In the logic well, a region of the first type of conductivity is formed, on which is formed a metallization, to implement, on the one hand, an ohmic contact, and on the other hand, a rectifying contact.
Claims41
A semiconductor device for providing a ground connection to a component, the component including a vertical MOS power transistor and logic components, the semiconductor device including:
- a substrate having a first conductivity type, the substrate corresponding to a drain of the MOS power transistor;
- a first well having a second conductivity type in an upper surface side of the substrate, the logic components being formed in the first well, the first well further including;
- a second well having the first conductivity type and a first doping level;
- and
- a first region having the first conductivity type and a second doping level greater than the first doping level, the first region being formed within the second well;
- and
- a metallization contacting the second well and the first region, the metallization forming an ohmic contact with the first region and a rectifying contact with the second well.
A semiconductor device, comprising:
- a substrate having a first conductivity type;
- a first well formed in the substrate, the first well having a second co pe and a first doping level;
- a second well formed in the first well, the second well having the first conductivity type and a second doping level;
- at least one first region formed in the second well, the at least one first region having the first conductivity type and having a third doping level greater than the second doping level;
- further including a first metallization contacting the at least one first region;
- wherein:
- the at least one first region includes a plurality of first regions;
- and
- the first metallization contacts each first region of the plurality of first regions.
A semiconductor device, comprising:
- a substrate having a first conductivity type;
- a first well formed in the substrate, the first well having a second conductivity type and a first doping level;
- a second well formed in the first well, the second well having the first conductivity type and a second doping level;
- at least one first region formed in the second well, the at least one first region having the first conductivity type and having a third doping level greater than the second doping level;
- further including a first metallization contacting the at least one first region;
- further including a plurality of second regions formed in the second well, the plurality of second regions having the second conductivity type.
A semiconductor device, comprising:
- a substrate having a first conductivity type;
- a first well formed in the substrate, the first well having a second conductivity type and a first doping level;
- a second well formed in the first well, the second well having the first conductivity type and a second doping level;
- at least one first region formed in the second well, the at least one first region having the first conductivity type and having a third doping level greater than the second doping level;
- further including a first metallization contacting the at least one first region;
- further including a plurality of second regions formed in the second well, the plurality of second regions having the second conductivity type
- further including a first logic component formed in the first well.
A semiconductor device, comprising:
- a substrate having a first conductivity type;
- a first well formed in the substrate, the first well having a second conductivity type an first doping level;
- a second well formed in the first well, the second well having the first conductivity type and a second doping level;
- at least one first region formed in the second well, the at least one first region having the first conductivity type and having a third doping level greater than the second doping level;
- further including a first metallization counting the at least one first region;
- wherein the first metallization further contacts at least a portion of the second well.
Dependencies are inferred from the claim text.