MOS gated device with self aligned cells
AssigneeInternational Rectifier Corporation
InventorDaniel M. Kinzer
Life of this patent
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Abstract
An MOS-gated power semiconductor device is formed by a process in which a self-aligned device cell is formed without any critical alignments. A sidewall spacer is used to mask the etching of a depression in the silicon to reduce the number of critical alignment steps. An optional selectively formed metal connects the polysilicon layer to the P+ and N+ diffusion regions. The sidewall spacer, in combination with the selectively formed metal, prevents impurities from diffusing to the parasitic DMOS channels and inverting them to cause leakage. A termination structure may also be formed by this process.
Claims15
A semiconductor device comprising:
- a layer of gate insulation material formed atop a silicon substrate of one conductivity type;
- a layer of polysilicon formed atop said layer of gate insulation material;
- a first overlaying insulation layer having a plurality of spaced openings therein;
- said layer of polysilicon having a further plurality of spaced openings therein that correspond to said plurality of spaced openings in said first overlaying insulation layer;
- first diffused regions of impurities of another conductivity type, which is of opposite conductivity type to said one conductivity type, formed in surface regions of said silicon substrate that are located beneath said further openings in said layer of polysilicon;
- second diffused regions of impurities of said one conductivity type formed in said surface regions of said silicon substrate;
- third diffused regions of said another conductivity type formed in said surface regions of said silicon substrate;
- said second diffused regions having a final depth that is less than that of said third diffused regions, said first diffused regions being deeper and wider than and having a lower concentration than that of said third diffused regions;
- a plurality of vertical sidewall spacers of a second overlaying insulation layer formed along sidewalls in each of said openings in said first overlaying insulation layer and along sidewalls in each of said further openings in said layer of polysilicon which surround a portion of each of said surface regions of said silicon substrate;
- a plurality of depressions formed in said portion of said surface regions of said silicon substrate and having a depth greater than the depth of said second diffused regions;
- and
- a contact conductive layer comprising at least one source contact which contacts said second and third diffused regions and at least one gate contact.
Dependencies are inferred from the claim text.