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US 6,144,057 AGranted
Semiconductor memory device including a field effect transistor
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorShunpei Yamazaki
Life of this patent
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Abstract
A semiconductor memory device including a field effect transistor associated with a semiconductor substrate and a capacitor. The capacitor is connected to a drain region of the transistor. Specifically, the capacitor includes a dielectric layer including a ferroelectric material. The capacitor is located above a gate electrode of the transistor and completely overlaps the gate electrode. The device may also include a pair of field effect transistors wherein each source of the transistors shares a common impurity doped region of the semiconductor substrate.
Claims19
A semiconductor memory device comprising:
- a semiconductor substrate;
- a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity doped region formed in a plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors;
- a first capacitor connected to a drain of one of said transistors;
- a second capacitor connected to a drain of another one of said transistors,
- wherein said each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, said dielectric layer comprising a ferroelectric material, and
- wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
3 more elements
A semiconductor memory device comprising:
- a semiconductor substrate;
- a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity doped region formed in a plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors;
- a first capacitor connected to a drain of one of said transistors;
- a second capacitor connected to a drain of another one of said transistors, and
- wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
2 more elements
A semiconductor memory device including at least first and second insulated gate field effect transistors, said device comprising:
- a semiconductor substrate having a first surface and a plateau elevated from said first surface;
- a first impurity region formed within said plateau as a source of both said first and second transistors;
- a pair of second impurity regions formed within said semiconductor substrate with said plateau disposed therebetween as drains of said first and second transistors, respectively;
- a pair of capacitors electrically connected to said pair of second impurity regions, respectively;
- a pair of channel regions formed within said substrate between said plateau and said pair of second impurity regions, respectively;
- and
- a pair of gate electrodes adjacent to said channel regions, respectively,
- wherein each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, said dielectric layer comprising a ferroelectric material, and
- wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
6 more elements
A semiconductor memory device comprising:
- a semiconductor substrate;
- a pair of field effect transistors associated with said semiconductor substrate, each of which comprises source and drain regions, a channel region therebetween, and a gate electrode over the channel region wherein the source regions of the pair of field effect transistors are formed in a same impurity region in a plateau elevated from said semiconductor substrate;
- a first capacitor connected to a drain region of one of the drains of the pair of transistors;
- a second capacitor connected to the other one of the drains of the pair of transistors;
- wherein each of said first and second capacitor has a dielectric layer, and
- wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
3 more elements
A semiconductor memory device including at least first and second insulated gate field effect transistors, said device comprising:
- a semiconductor substrate having a first surface and a plateau elevated from said first surface;
- a first impurity region formed within said plateau as a source of both said first and second transistors;
- a pair of second impurity regions formed within said semiconductor substrate with said plateau disposed therebetween as drains of said first and second transistors, respectively;
- a pair of capacitors electrically connected to said pair of second impurity regions, respectively;
- a pair of channel regions formed within said substrate between said plateau and said pair of second impurity regions, respectively;
- and
- a pair of gate electrodes adjacent to said channel regions, respectively,
- wherein each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, and
- wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
6 more elements
A semiconductor memory device comprising:
- a semiconductor substrate;
- a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity region formed in plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors;
- a first capacitor connected to a drain of one of said transistors;
- a second capacitor connected to a drain of another one of said transistors, wherein each of said first and second capacitors comprises a pair of electrodes and a tantalum oxide layer interposed therebetween, and
- wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
2 more elements
A semiconductor memory device comprising:
- a semiconductor substrate;
- a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity region formed in plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors;
- a first capacitor connected to a drain region of said drain regions of said pair of transistors;
- a second capacitor connected to the other one of said drains of said pair of transistors;
- wherein each of said first and second capacitors has a dielectric layer comprising tantalum oxide, and
- wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
3 more elements
Dependencies are inferred from the claim text.