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US 6,144,055 AGranted
Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorHiroyuki Takenaka
Life of this patent
Estimating the term…
Abstract
A dynamic memory device includes a buried plate-wiring connected to a plate electrode of a memory cell. A plate potential is supplied to the buried plate-wiring via a plate potential supply-wiring. A connection node of the buried plate-wiring and the plate potential supply-wiring is arranged at a side of the memory cell array opposed to a side of a row decoder array.
Claims21
A semiconductor memory device comprising:
- a semiconductor substrate having a memory cell array which includes a plurality of memory cells arranged in a matrix;
- a first word line having a first portion located in the memory cell array and a second portion located out of the memory cell array;
- a second word line located above said first word line;
- a tap region provided in said second portion of said first word line, said tap region connecting said second word line to said first word line;
- and
- a plurality of trench capacitors located in said memory cell array and out of said memory cell array, those of said trench capacitors which are located in said memory cell array constituting elements of said memory cells,
- wherein said tap region is located above at least one of those of said trench capacitors which is located out of said memory cell array.
4 more elements
A semiconductor memory device comprising:
- a semiconductor substrate having a memory cell array which includes a plurality of memory cells arranged in a matrix;
- a word line having a first portion located in the memory cell array and a second portion located out of the memory cell array;
- a wiring line located above said word line;
- a tap region provided in said second portion of said word line, said tap region connecting said wiring line to said word line;
- and
- a plurality of trench capacitors located in said memory cell array and out of said memory cell array, those of said trench capacitors which are located in said memory cell array constituting elements of said memory cells,
- wherein said tap region is located above at least one of those of said trench capacitors which is located out of said memory cell array.
4 more elements
Dependencies are inferred from the claim text.