Method of reducing metal voidings in 0.25 .mu.m AL interconnect
AssigneeAdvanced Micro Devices, Inc.
InventorsMinh Van Ngo, Simon S. Chan, Suzette K. Pangrle, Robert A. Huertas
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AssigneeAdvanced Micro Devices, Inc.
InventorsMinh Van Ngo, Simon S. Chan, Suzette K. Pangrle, Robert A. Huertas
Estimating the term…
In one embodiment, the present invention relates to a method of depositing a dielectric layer over a stacked interconnect structure, involving the steps of: providing a substrate having at least one stacked interconnect structure comprising at least one of an aluminum layer and an aluminum alloy layer; depositing the dielectric layer over the stacked interconnect structure under a pressure from about 1 mTorr to about 6 mTorr, an O.sub.2 flow rate from about 110 sccm to about 130 sccm and a silane flow rate from about 52 sccm to about 60 sccm at a bias power from about 2500 W to about 3100 W, under a pressure from about 2 Torr to about 2.8 Torr, an N.sub.2 flow rate from about 7 l to about 11.5 l, an N.sub.2 O flow rate from about 1 l to about 2 l and a silane flow rate from about 250 sccm to about 300 sccm at a power from about 900 W to about 1300 W at a temperature from about 300.degree. C. to about 350.degree. C., or under a pressure from about 2 Torr to about 2.8 Torr, an N.sub.2 flow rate from about 7 l to about 11.5 l, an N.sub.2 O flow rate from about 1 l to about 2 l and a silane flow rate from about 80 sccm to about 120 sccm at a power from about 900 W to about 1300 W at a temperature from about 390.degree. C. to about 410.degree. C.
A method of depositing a dielectric layer over a stacked interconnect structure, comprising:
A method of reducing formation of voidings in a stacked interconnect structure comprising a titanium layer adjacent a layer comprising aluminum, comprising:
A method of depositing a silicon dioxide interlayer dielectric layer over a stacked interconnect structure, comprising:
Dependencies are inferred from the claim text.