KLXX technology with integrated passivation process, probe geometry and probing process

A method of coupling an integrated circuit chip to a chip package comprising:

• providing an integrated circuit having a bond pad, a first passivation layer overlying a top surface of said bond pad, and a second passivation layer overlying said first passivation layer;
• exposing an area portion of said top surface of said bond pad of said integrated circuit, by
• a) removing a portion of said second passivation layer above said area portion of said bond pad;
• b) after removing a portion of said second passivation layers curing said second passivation layer;
• and
• c) after curing, etching a portion of said exposed area of said first passivation layer to expose said area portion of said bond pad;
• and
• coupling said integrated circuit to a chip package through said bond pad.

A method of probing the bond pads of an integrated circuit, comprising:

• exposing an area portion of adjacent bond pads of an integrated circuit, said adjacent bond pads having a pad pitch less than 80 microns;
• and
• probing said adjacent bond pads with a probe card,
• wherein said integrated circuit has a first passivation layer overlying said area portion of each of said bond pads, and a second passivation layer overlying said first passivation layer, and exposing an area portion of adjacent bond pads comprises:
• removing a portion of said second passivation layer to expose an area of said first passivation layer above a portion of said area portion of each of said pads;
• after removing a portion of said second passivation layer, curing said second passivation layer;
• and
• after curing, etching a portion of said exposed area of said first passivation layer to expose said top surface of said bond pad.