Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation
AssigneeMotorola, Inc.
InventorJeffrey Thomas Wetzel
Life of this patent
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Abstract
A method for forming a dual inlaid contact structure (damascene) begins by etching dual inlaid contact structures (32, 34, and 36). Masking layers (28) are (228) and the deposition of low-K dielectric material 26 is used to selectively form low-K regions (30) only in critical areas where low-K dielectric material is absolutely needed. Other portions of the wafer remain covered with conventional oxide (24) so that adverse impacts of low-K dielectric material is minimized. Conductive material (38, 40, and 42) is then formed to complete dual inlaid contact structures whereby low-K dielectric plugs (30) reduce cross talk and capacitance within the final structure.
Claims20
A method for forming an integrated circuit structure, the method comprising the steps of:
- forming a first dielectric region wherein the first dielectric region is patterned to have an opening having a first sidewall opposite a second sidewall, the first dielectric region comprising a first dielectric material having a first dielectric constant;
- etching a portion of the first dielectric material laterally adjacent the second sidewall of the opening to form a void region;
- filling the void region with a second dielectric region which has a second dielectric constant that is less than the first dielectric constant;
- and
- filling the opening with a conductive material to form a conductive interconnection, the conductive interconnection having a first sidewall in contact with the first sidewall of the opening and a second sidewall in contact with the second sidewall of the opening.
A method for forming a contact structure, the method comprising the steps of:
- forming a first dielectric region wherein the first dielectric region is patterned to have an opening having a first sidewall opposite a second sidewall;
- filling a middle portion of the opening with a low-K dielectric;
- filling a portion of the opening on a first side of the middle portion with a first conductive interconnection;
- and
- filling a portion of the opening on a second side of the middle portion with a second conductive interconnection.
A method for forming a contact structure, the method comprising the steps of:
- forming a first dielectric layer;
- forming an etch stop layer overlying the first dielectric layer;
- forming a second dielectric layer overlying the first dielectric layer;
- etching openings into the second dielectric layer;
- etching the openings to deepen the openings through the first dielectric layer while also forming interconnect openings in the second dielectric layer resulting in a dual-in-laid structure;
- depositing a low-K dielectric material within the interconnect openings;
- processing the low-K dielectric material to remove portions of the low-K dielectric material in the interconnect openings to form a low-K dielectric middle portion;
- depositing a conductive material;
- and
- processing the conductive material to form a first conductive interconnect within the interconnect opening and adjacent a first sidewall of the low-K dielectric middle portion and a second conductive interconnect within the interconnect opening and adjacent a second sidewall of the low-K dielectric middle portion, whereby the low-K dielectric middle portion separates the first and second conductive interconnects.
A method for forming a contact structure, the method comprising the steps of:
- forming a first dielectric layer;
- forming an etch stop layer overlying the first dielectric layer;
- forming a second dielectric layer overlying the first dielectric layer;
- etching interconnect openings into the second dielectric layer;
- etching contact openings into the first dielectric layer wherein the contact openings lie within the interconnect openings thereby resulting in a dual-in-laid structure;
- depositing a low-K dielectric material within the interconnect openings;
- processing the low-K dielectric material to remove portions of the low-K dielectric material in the interconnect openings to form a low-K dielectric middle portion;
- depositing a conductive material;
- and
- processing the conductive material to form a first conductive interconnect within the interconnect opening and adjacent a first sidewall of the low-K dielectric middle portion and a second conductive interconnect within the interconnect opening and adjacent a second sidewall of the low-K dielectric middle portion whereby the low-K dielectric middle portion separates the first and second conductive interconnects.
A method for forming a contact structure, the method comprising the steps of:
- forming a first dielectric layer;
- forming an etch stop layer overlying the first dielectric layer;
- forming a second dielectric layer overlying the etch stop layer;
- etching contact openings through the first dielectric layer, and interconnect openings through the second dielectric layer to form a first dual in-laid interconnect structure and a second dual in-laid interconnect structure laterally adjacent one another, the contact openings being surrounded by the first dielectric layer and the interconnect openings being separated by a second dielectric layer middle portion;
- forming a masking layer within the first and second dual in-laid interconnect structures;
- forming an opening through the masking layer which exposes a portion of the second dielectric layer middle portion;
- etching a portion of the second dielectric layer middle portion between the first and second dual in-laid interconnect structure to form a void region;
- and
- forming a low-K dielectric within the void region whereby a low-K dielectric plug is positioned between the first and second dual in-laid interconnect structure.
A method for forming a semiconductor structure, the method comprising the steps of:
- forming a photoresist layer;
- forming a low-K dielectric material over the photoresist layer;
- and
- chemical mechanically polishing top portions of both the low-K dielectric material and the photoresist layer to form a planar top surface.
Dependencies are inferred from the claim text.