US 6,143,613 AGranted

Selective exclusion of silicide formation to make polysilicon resistors

AssigneeVLSI Technology, Inc.

InventorXi-Wei Lin

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Abstract

A technique for processing an integrated circuit is disclosed. This technique includes the formation of a polysilicon resistor without silicide next to a polysilicon transistor gate with silicide. Prior to silicidation, an oxide layer coats both polysilicon structures. A portion of the oxide layer is removed by chemical-mechanical polishing to define a generally planar surface from the remaining oxide layer and reexposed portions of each polysilicon structure. A metal layer is deposited on the surface. The portion of the metal layer over the polysilicon resistor structure is removed through a lithographic procedure. A self-aligned silicidation procedure is performed to form a silicide from the metal remaining over the polysilicon gate structure. The formation of both structures is then completed.

Claims24

Dependent claims

A process for manufacturing an integrated circuit, comprising the steps of:

(a) defining a region of a silicon substrate for formation of a polysilicon resistor adjacent a field effect transistor, the region including a first structure extending from the substrate spaced apart from a second structure extending from the substrate, the first and second structure each including a polysilicon strip on an oxide pad, the oxide pad being positioned between the polysilicon strip and the substrate, The first structure being bounded by a first spacer wall and the second structure being bounded by a second spacer wall separated from the first spacer wall along the substrate to define a gap therebetween;
(b) depositing a silicon dioxide layer on the region, the silicon dioxide layer covering the first and second structures and filling the gap;
(c) removing a portion of the silicon dioxide layer by chemical mechanical polishing to expose the polysilicon strip of each the first and second structures, the silicon dioxide layer remaining in the gap after said removing and the polysilicon strip of each of the first and second structures defining a generally planar surface;
(d) providing a metallic layer covering the generally planar surface;
(e) establishing a photoresist pattern on the metallic layer, the photoresist pattern defining an opening over the first structure and covering the second structure;
(f) etching the metallic layer to remove a portion of the metallic layer corresponding to the opening over the first structure to reexpose the polysilicon strip of the first structure;
(g) stripping the photoresist pattern;
(h) performing a self-aligned silicidation process to define a silicide layer from a portion of the polysilicon strip of the second structure;
and
(i) completing formation of the polysilicon resistor from the first structure and the field effect transistor from the second structure.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/885,378Filed 30 Jun 1997
Granted: 7 Nov 2000
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 1/47
Resistors: resistors having no potential barriers
H10D 30/0213
Using self-aligned silicidation: providing different silicide thicknesses on gate electrodes and on source regions or drain regions
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 64/0131
The conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of…: the…