Debug interface including data steering between a processor, an input/output port, and a trace logic
AssigneeAdvanced Micro Devices, Inc.
InventorVenkateswara Rao Madduri
Life of this patent
Estimating the term…
Abstract
A system for debugging a processor includes a data steering circuit for steering commands and data from a debug port and a parallel input/output port. The data steering circuit also directs commands and data to from the debug port and the parallel input/output port to the same set of debug registers. The data steering circuit also selectively directs trace information indicative of execution of instructions in the processor to either a trace buffer or directly out to a port, such as the debug port or the parallel input/output port.
Claims23
A processor comprising:
- a processor core within the processor and responsive to instructions to perform processing operations;
- a parallel input/output port coupled to the processor core and communicating information between an external device and the processor core;
- a debug port coupled to the processor core and communicating debug information between a debug device and the processor;
- a common decode logic coupled to the processor core, the parallel input/output port, and the debug port for decoding commands from the parallel input/output port and the debug port;
- and
- a data steering logic coupled to the processor core, the parallel input/output port, and the debug port, the data steering logic selectively steering commands and data from either the parallel input/output port or the debug port to the common decode logic.
A debug interface for interfacing a processor to a debug device, the debug interface comprising:
- an input/output port;
- a buffer coupled to the processor;
- a data steering controller coupled to the processor, the input/output port, and the buffer, the data steering controller directing data from the processor to either the input/output port or the buffer depending on the content of the buffer.
A debug interface for interfacing a processor to an external debug device, the debug interface comprising:
- a debug port coupled to the processor and including a plurality of pins for communicating signals with the external debug device;
- a parallel input/output port coupled to the processor and including a plurality of pins for communicating signals with the external debug device;
- a decode logic coupled to the debug port and the parallel input/output port, the decode logic for decoding debug commands and data received both from the debug port and the parallel input/output port;
- and
- a data steering controller coupled to the debug port, the parallel input/output port, and the decode logic, the data steering controller including a debug port state machine and a parallel port state machine, the data steering controller selectively directing data between the processor and the debug port, and between the processor and the parallel input/output port.
Dependencies are inferred from the claim text.