Power reduction in a multiprocessor digital signal processor based on processor load
OwnerChristopher J. Nicol, Kanwar Jit Singhinventors
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OwnerChristopher J. Nicol, Kanwar Jit Singhinventors
Estimating the term…
Improved operation of multi-processor chips is achieved by dynamically controlling processing load of chips and controlling, significantly greater than on/off granularity, the operating voltages of those chips so as to minimize overall power consumption. A controller in a multi-processor chip allocates tasks to the individual processors to equalize processing load among the chips, then the controller lowers the clock frequency on the chip to as low a level as possible while assuring proper operation, and finally reduces the supply voltage. Further improvement is possible by controlling the supply voltage of individual processing elements within the multi-processor chip, as well as controlling the supply voltage of other elements in the system within which the multi-processor chip operates.
A method executed within a system for controlling power consumption of a sub-circuit of said system comprising the steps of:
A circuit that includes a processor, comprising:
A circuit comprising:
A circuit that includes a processor, comprising:
A method for operating a processor comprising the step of applying a supply voltage to said processor as a function of frequency necessary to operate said processor to complete an assigned task within an assigned time interval.
Dependencies are inferred from the claim text.