Apparatus and method for microcode patching for generating a next address

A method of patching microcode instructions comprising:

• receiving an entry point address generated in response to a first fetched instruction;
• accessing a microcode instruction corresponding to said first fetched instruction using said entry point address;
• accessing a flag bit associated with said microcode instruction using said entry point address;
• if said flag bit is deasserted, dispatching said microcode instruction;
• and
• if said flag bit is asserted, branching to a patch microcode routine, dispatching microcode instructions within said patch microcode routine that store a substitute microcode instruction corresponding to said first fetched instruction in a data register, and dispatching said substitute microcode instruction instead of said microcode instruction.

A microprocessor comprising:

• an instruction cache;
• a first instruction unit coupled to said instruction cache;
• a microcode instruction unit coupled to said instruction cache to receive a first fetched instruction fetched from said instruction cache, said microcode instruction unit including:
• a first memory for storing microcode instructions, wherein said first memory stores a patch microcode routine;
• a second memory for storing a plurality of flag bits, wherein different ones of said plurality of flag bits are associated with different ones of said microcode instructions;
• an address generator coupled to said first memory, wherein said address generator generates, in response to said first fetched instruction, an entry point address of a first microcode instruction within said first memory, said first microcode instruction corresponding to said first fetched instruction, wherein said first memory is configured to provide said first microcode instruction in response to said entry point address, and wherein said second memory is configured to provide a first flag bit of said plurality of flag bits in response to said entry point address;
• and
• a controller coupled to said first memory and said second memory, wherein if said first flag bit associated with said first microcode instruction is asserted, said controller:
• branches to said patch microcode routine;
• dispatches a second microcode instruction within said patch microcode routine that stores a substitute microcode instruction corresponding to said first fetched instruction in a data register;
• and dispatches said substitute microcode instruction instead of said first microcode instruction;
• a decode unit coupled to said first instruction unit and said microcode instruction unit;
• and
• one or more functional units coupled to said decode unit.

A computer system comprising:

• a microprocessor including:
• an instruction cache;
• and
• a microcode instruction unit coupled to said instruction cache to receive a first fetched instruction fetched from said instruction cache, said microcode instruction unit including:
• a first memory for storing microcode instructions, wherein said first memory stores a patch microcode routine;
• a second memory for storing a plurality of flag bits, wherein different ones of said plurality of flag bits are associated with different ones of said microcode instructions;
• an address generator coupled to said first memory, wherein said address generator generates, in response to said first fetched instruction, an entry point address of a first microcode instruction within said first memory, said first microcode instruction corresponding to said first fetched instruction, wherein said first memory is configured to provide said first microcode instruction in response to said entry point address, and wherein said second memory is configured to provide a first flag bit of said plurality of flag bits in response to said entry point address;
• and
• a controller coupled to said first memory and said second memory, wherein if said first flag bit associated with said first microcode instruction is asserted, said controller:
• branches to said patch microcode routine;
• dispatches a second microcode instruction within said patch microcode routine that stores a substitute microcode instruction corresponding to said first fetched instruction in a data register;
• and dispatches said substitute microcode instruction instead of said first microcode instruction;
• and
• an input/output (I/O) device coupled to said microprocessor and to another computer system, wherein said I/O device is configured to communicate between said computer system and said another computer system.