Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including same

A memory cell having first and second operating modes, comprising:

• a transistor comprising a gate adjacent to a channel region coupling source and drain regions;
• a digitline coupled to one of the source and drain regions;
• a storage capacitor coupled to the other of the source and drain regions,
• a ferroelectric capacitor;
• and
• a wordline coupled to the gate by the ferroelectric capacitor,
• wherein data is written to and read out of the storage capacitor during the first operating mode and written to and read out of the ferroelectric capacitor during the second mode of operation.

A memory cell storing first and second data types, comprising:

• a transistor comprising a gate opposing a channel region coupling source and drain regions;
• a digitline coupled to one of the source and drain regions;
• a storage capacitor, which stores the first type of data, coupled to the other of the source and drain regions,
• a ferroelectric capacitor, which stores the second type of data;
• and
• a wordline coupled to the gate by the ferroelectric capacitor.

A memory cell array which stores first and second data types in first and second data storage planes, respectively, comprising:

• a plurality of memory cells organized as an array of rows and columns, at least one of the memory cells comprising:
• a transistor comprising a gate opposing a channel region coupling source and drain regions;
• a digitline coupled to one of the source and drain regions;
• a storage capacitor, which stores the first type of data, coupled to the other of the source and drain regions,
• a ferroelectric capacitor, which stores the second type of data;
• and
• a wordline coupled to the gate by the ferroelectric capacitor;
• and
• a sense amplifier coupled to the digitline of the at least one memory cell.

A processor based system, comprising:

• a processor;
• and
• a memory cell array coupled to the processor, the memory cell array storing first and second data types in first and second data storage planes, respectively, the memory cell array including a plurality of memory cells organized as an array of rows and columns, at least one of the memory cells comprising:
• a transistor comprising a gate opposing a channel region coupling source and drain regions;
• a digitline coupled to one of the source and drain regions;
• a storage capacitor, which stores the first type of data, coupled to the other of the source and drain regions,
• a ferroelectric capacitor, which stores the second type of data;
• a wordline coupled to the gate by the ferroelectric capacitor;
• and
• a sense amplifier coupled to the digitline of the at least one memory cell.

A memory module, comprising:

• a substrate comprising a circuit board;
• a plurality of memory chips mounted on the substrate, wherein one or more of the memory chips comprise a memory cell array fabricated on the semiconductor chip communicating with a processor, said memory cell array comprising:
• a plurality of one transistor/two capacitor (1T/2C) memory cells, wherein the 1T/2C memory cell comprises:
• a transistor comprising a gate adjacent to a channel region coupling source and drain regions;
• a digitline coupled to one of the source and drain regions;
• a storage capacitor coupled to the other of the source and drain regions, a ferroelectric capacitor;
• and a wordline coupled to the gate by the ferroelectric capacitor,
• wherein each of the 1T/2C memory cells has first and second modes of operation, the first mode of operation accessing said first capacitor and the second operating mode accessing said second capacitor.

A method for forming a memory cell, said method comprising:

• forming source and drain regions in a substrate well;
• forming a gate between said source and drain regions;
• forming a first ferroelectric capacitor on said gate with a first conductor of said ferroelectric capacitor coupled to said gate;
• forming a wordline conductor on a second conductor of said ferroelectric capacitor;
• and
• forming a second capacitor having one conductor electrically coupled to one of said source and drain regions.