Ferroelectric non-volatile latch circuits
AssigneeRamtron International Corporation
InventorsJarrod Eliason, William F. Kraus
Life of this patent
Estimating the term…
Abstract
A non-volatile ferroelectric latch includes a sense amplifier having at least one input/output coupled to a bit-line node, a ferroelectric storage capacitor coupled between a plate-line node and the bit-line node, and a load element coupled to the bit-line node. The sense amplifier further includes a second input/output coupled to a second bit-line node and the latch further includes a second ferroelectric storage capacitor coupled between a second plate-line node and the second bit-sine node, and a second load element coupled to the second bit-line node. The load element includes a dynamic, switched ferroelectric capacitor a static, nonswitched ferroelectric capacitor, a linear capacitor, or even a resistive load.
Claims29
A non-volatile ferroelectric latch comprising:
- a sense amplifier having first and second input/outputs coupled respectively coupled to first and second internal bit-line nodes;
- a pair of balanced ferroelectric capacitors coupled between the first and second internal bit-line nodes;
- and
- isolation circuitry coupled between the first and second internal bit-line nodes and first and second external bit-line nodes.
The non-volatile ferroelectric latch comprising:
- a sense amplifier having first and second input/outputs coupled respectively coupled to first and second internal bit-line nodes;
- a first ferroelectric capacitor coupled between a first plate-line node and the first internal bit-line node;
- a second ferroelectric capacitor coupled between a second plate-line node and the second internal bit-line node;
- a first load element coupled between the first internal bit-line node and ground;
- a second load element coupled between the second internal bit-line node and ground;
- control circuitry coupled to the first and second plate-line nodes and to the first and second internal bit-line nodes;
- and
- isolation circuitry coupled between the first and second internal bit-line nodes and the first and second external bit-line nodes.
The non-volatile ferroelectric latch comprising:
- a sense amplifier having first and second input/outputs respectively coupled to first and second internal bit-line nodes;
- a first ferroelectric capacitor coupled between a first plate-line node and the first internal bit-line node;
- a second ferroelectric capacitor coupled between the first plate-line node and the second internal bit-line node;
- a first load element coupled between the first internal bit-line node and a second plate-line node;
- a second load element coupled between the second internal bit-line node and the second plate-line node;
- and
- isolation circuitry coupled between the first and second internal bit-line nodes and the first and second external bit-line nodes.
The non-volatile ferroelectric latch comprising:
- a first controlled sense amplifier having first and second input/outputs respectively coupled to first and second internal bit-line nodes;
- a second controlled sense amplifier having first and second input/outputs respectively coupled to first and second plate-line nodes;
- a first ferroeiectric capacitor coupled between the first plate-line node and the first internal bit-line node;
- a second ferroelectric capacitor coupled between the second plate-line node and the second internal bit-line node;
- a first load element coupled between the first internal bit-line node and ground;
- a second load element coupled between the second internal bit-line node and ground;
- and
- isolation circuitry coupled between the first and second internal bit-line nodes and first and second external bit-line nodes.
A non-volatile ferroelectric latch comprising:
- a sense amplifier having at least one input/output coupled to a bit-line node;
- a ferroelectric storage capacitor coupled between a plate-line node and the bit-line node;
- and
- a load element coupled to the bit-line node.
The non-volatile ferroelectric latch comprising:
- a pair of isolated plate lines;
- a sense amplifier having a pair of input/output nodes respectively coupled to the pair of plate lines;
- a pair of ferroelectric capacitors respectively coupled between the plate lines and a pair of bit line nodes;
- a load element pair coupled to the pair of bit line nodes;
- and
- circuitry for providing a complementary data state to the pair of bit line nodes.
Dependencies are inferred from the claim text.